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数据搜索系统，热门电子元器件搜索 |
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CSG14K_CSG8K 数据表(PDF) 30 Page - OSRAM GmbH |
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CSG14K_CSG8K 数据表(HTML) 30 Page - OSRAM GmbH |
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30 / 114 page  Document Feedback CSG14K_CSG8K Functional Description Datasheet • PUBLIC DS000571 • v2-01 • 2023-Feb-10 113 │ 29 Figure 23: SPI Read Timing Register Banks The sensor’s configuration registers are organized in five banks. Each bank contains 124, 8-bit registers. To select a certain register bank, the register at address 0 is used. Address 0 is always accessible, regardless of the currently selected register bank. Figure 24: Bank Selection Register Register Name Bit Name Bank Addr Pos Description BANK_SEL BANK_SEL N/A 0 [2:0] 0: Bank 0 1: Bank 1 2: Bank 2 3: Bank 3 4: Bank 4 The value of BANK_SEL selects which register bank the current SPI access will have an effect on. The Block ID Inside the sensor, there are different blocks that each hold a unique copy of the register banks. The different blocks are the sequencers (A and B) and the DPPs for the output channels (VIS + OB). All of these blocks are connected to the SPI interface and are addressed with a unique identifier called the BLOCK_ID. Figure 27 shows the organization of all blocks in the sensor along with their BLOCK IDs. The sensor’s SPI interface is distributed internally towards all blocks. The BLOCK_SEL register, located at address 1, determines which block is accessed by future SPI transactions. For example, when the BLOCK_SEL register is set to 0, all SPI read SPI_CLK SPI_CSN SPI_MOSI C= ’0' A[6] A[5] A[4] A[3] A[2] A[1] A[0] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] ctrl address data (N) SPI_MISO Hi-Z D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] data (N+1) Hi-Z C= ’0' A[6] A[5] A[4] A[3] A[2] A[1] A[0] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] ctrl address data Hi-Z Hi-Z SPI_CLK SPI_CSN SPI_MOSI SPI_MISO x x ½ Tspi ½ Tspi |
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