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CSG14K_CSG8K 数据表(PDF) 70 Page - OSRAM GmbH |
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CSG14K_CSG8K 数据表(HTML) 70 Page - OSRAM GmbH |
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70 / 114 page ![]() Document Feedback CSG14K_CSG8K Functional Description Datasheet • PUBLIC DS000571 • v2-01 • 2023-Feb-10 113 │ 69 Set Row Length The ROW_LENGTH register sets the line rate of the sensor. The required setting of this parameter is dependent on different sensor operation modes – which are known at this stage of the configuration procedure. The maximum frame time is achieved when the ROW_LENGTH register is set to its minimal allowed value as per below equation. ROW_LENGTH Register Limitation Equation 3: ROW_LENGTH ≥ max(������������������_������������������������������������������������������, ������������������������������ + 12) Where KSIZE refers to the register value and ROW_LENGTHmin is image mode dependent (see Figure 62). Refer to section 7.5.2 for further details on this register. Set Control Mode Depending on the selected sensor control mode (see 7.4.2), the following SPI register settings must be written. Refer to section 7.2.7 for a detailed description of the control modes. Figure 79: Control Mode Register Register Bank Address SEN.1 SEN.2 SEN.3 SEN.4 CTRL_MODE 0 11 0 1 2 3 SEN.1 (Full External) provides maximal freedom to the user as all exposure and frame control is external to the sensor. It is also the most complex mode, as the user is responsible for generating correct timing of the request pulses (REQ_EXP and REQ_FRAME). The other control modes each add a little intelligence to the sensor, making it easier for the user to control the frame acquisition. When choosing the sensor control mode, it is important to consider the latency between the external REQ_EXP request and the start of the first exposure on the image array. The SEN.2, SEN.3 and SEN.4 control modes all have an additional latency of 1 Time Unit. The SEN.1 control mode does not have this additional latency. Release Soft Reset Once the PLLs are locked, the sensor can be released from soft reset and the main clock can be enabled, by applying the following register write sequence. |
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