PPC405EP – PowerPC 405EP Embedded Processor

Revision 1.07 – September 10, 2007

AMCC

29

Data Sheet

Signal List

The following table provides a summary of the number of package pins associated with each functional interface

group.

In the table “Signal Functional Description” on page 31, each external signal is listed along with a short description

of the signal function. Active-low signals (for example, RAS) are marked with an overline. Please see “Signals

Listed Alphabetically” on page 13 for the pin (ball) number to which each signal is assigned.

Multiplexed Pins

Some signals are multiplexed on the same package pin (ball) so that the pin can be used for different functions. In

most cases, the signal names shown in this table are not accompanied by signal names that may be multiplexed

on the same pin. If you need to know what, if any, signals are multiplexed with a particular signal, look up the name

in “Signals Listed Alphabetically” on page 13. It is expected that in any single application a particular pin will always

be programmed to serve the same function. The flexibility of multiplexing allows a single chip to offer a richer pin

selection than would otherwise be possible.

In addition to multiplexing, many pins are also multi-purpose. For example, in the PCI interface PCIC3:0/BE3:0

serves as both Command and Byte Enable signals. In this example, the pins are also bidirectional, serving as both

inputs and outputs.

Initialization Strapping

One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only

during reset and are used for other functions during normal operation (see “Initialization” on page 48). Note that the

use of these pins for strapping is not considered multiplexing since the strapping function is not programmable.

Pull-Up and Pull-Down Resistors

Pull-up and pull-down resistors are used for strapping during reset and to retain unused or undriven inputs in an

appropriate state. The recommended pull-up value of 3k

Ω to +3.3V (10kΩ to +5V can be used on 5V tolerant I/Os)

and pull-down value of 1k

Ω to GND, applies only to individually terminated signals. To prevent possible damage to

the device, I/Os capable of becoming outputs must never be tied together and terminated through a common

resistor.

If your system-level test methodology permits, input-only signals can be connected together and terminated

through either a common resistor or directly to +3.3V or GND. When a resistor is used, its value must ensure that

the grouped I/Os reach a valid logic zero or logic one state when accounting for the total input current into the

PPC405EP.

Table 5. Pin Summary

Group

No. of Pins

Non multiplexed

215

Multiplexed

33

Total Signal Pins

248

43

16

Gnd

53

Thermal (and Gnd)

25

Reserved

0

Total Pins

385