PPC405EP datasheet(42/50 Pages) AMCC

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PPC405EP – PowerPC 405EP Embedded Processor

AMCC

Revision 1.07 – September 10, 2007

Data Sheet

Spread Spectrum Clocking

Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC405EP. This controller

uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to

as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the

SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the

PPC405EP the following conditions must be met:

•

The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the

PPC405EP with one or more internal clocks at their maximum supported frequency, the SSCG can only

lower the frequency.

•

The maximum frequency deviation cannot exceed

−3%, and the modulation frequency cannot exceed

40kHz. In some cases, on-board PPC405EP peripherals impose more stringent requirements (see Note 1).

•

Use the peripheral bus clock (PerClk) for logic that is synchronous to the peripheral bus since this clock

tracks the modulation.

•

Use the SDRAM MemClkOut since it also tracks the modulation.

Notes:

1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of approx-

imately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that the

connected device is running at precise baud rates. If an external serial clock is used the baud rate is unaf-

fected by the modulation.

2. Operation of the PPC405EP PCI Bridge is unaffected by the use of an SSCG.

The PCI controller must be operated in asynchronous mode. When in asynchronous mode, the PCI bus clock

must be driven into the PPC405EP PCIClk input. In this configuration the PCI controller supports the

66.66 MHz PCI clock specification which specifies a maximum frequency deviation of -1% at a modulation of

between 30 kHz and 33 kHz.

3. Ethernet operation is unaffected.

4. IIC operation is unaffected.

Caution: It is up to the system designer to ensure that any SSCG used with the PPC405EP meets the above

requirements and does not adversely affect other aspects of the system.

PPC405EP 数据表(PDF) 42 Page - Applied Micro Circuits Corporation

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