PPC405EP datasheet(48/50 Pages) AMCC

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PPC405EP – PowerPC 405EP Embedded Processor

AMCC

Revision 1.07 – September 10, 2007

Data Sheet

Initialization

The following describes the method by which initial chip settings are established when a system reset occurs.

Strapping

When the SysReset input is driven low (system reset), the state of certain I/O pins is read to enable default initial

conditions prior to PPC405EP start-up. The actual capture instant is the nearest system clock edge before the

deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0)

resistors to select the desired default conditions. The recommended pull-up is 3k

Ω to +3.3V or 10kΩ to +5V. The

recommended pull-down is 1K

Ω to GND. These pins are use for strap functions only during reset. They are used

for other signals during normal operation. The following table lists the strapping pins along with their functions and

strapping options. The signal names assigned to the pins for normal operation appear below the pin number.

EEPROM

During reset, configuration values other than the internal default values can be read from a serial EEPROM

connected to the IIC port. The association of bits in the EEPROM with the configuration values and their default

values are covered in detail in the PowerPC 405EP Embedded Processor User’s Manual.

Note: If P04 is strapped to 1, and the EEPROM is not connected or is defective, the PPC405EP remains in the

reset state and will not boot.

Table 16. Strapping Pin Assignments

Function

Option

Ball Strapping

IIC EEPROM controller

If the controller is enabled, 32 bytes of configuration data

are read from the EEPROM.

P04

UART0_Tx

Disable

Enable

EEPROM address (P04 = 1)

Boot ROM width (P04 = 0)

N02

UART0_RTS

Y17

SysErr

When P04 = 1, these pins set the high-order two

bits of the EEPROM base address.

High order EEPROM base address bits

Address bit

When P04 = 0, these pins indicated the width of

the boot ROM.

8 bits

16 bits

reserved

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