PPC405EP datasheet(46/50 Pages) AMCC

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PPC405EP – PowerPC 405EP Embedded Processor

AMCC

Revision 1.07 – September 10, 2007

Data Sheet

Internal Peripheral Interface

IICSCL

15.3

10.2

IICSDA

15.3

10.2

UART0_CTS

UART0_RTS

10.3

7.1

UART0_Rx

nananana

UART0_Tx

10.3

7.1

UART1_Rx

nananana

UART1_Tx

10.3

7.1

Interrupts Interface

[IRQ0:6]

10.3

7.1

JTAG Interface

TCK

nananana

async

TDI

async

TDO

10.3

7.1

async

TMS

nananana

async

TRST

async

System Interface

GPIO00:31

10.3

7.1

Halt

async

SysErr

10.3

7.1

async

SysReset

10.3

7.1

async

TestEn

async

[RejectPkt0:1]

async

SysClk

Table 14. I/O Specifications—Group 1 (Sheet 2 of 2)

Notes:

1. PCI timings are for asynchronous operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns

for 33.33MHz.

2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Timing shown is with EMAC noise filter

selected. See the CPC0_EPCTL register PowerPC 405EP Embedded Processor User’s Manual.

3. For PCI, IOH is specified at 0.9OVDD and IOL is specified at 0.1OVDD. For all other interfaces, IOH is specified at 2.4V and IOL

is specified at 0.4V.

Signal

Input (ns)

Output (ns)

Output Current (mA)

Clock

Notes

Setup Time

(TIS min)

Hold Time

(TIH min)

Valid Delay

(TOV max)

Hold Time

(TOH min)

IOH

(min)

IOL

(min)

PPC405EP 数据表(PDF) 46 Page - Applied Micro Circuits Corporation

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PPC405EP 数据表(PDF) 46 Page - Applied Micro Circuits Corporation

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