PPC405EP datasheet(5/50 Pages) AMCC

部件名	PPC405EP

功能描述	PowerPC 405EP Embedded Processor

PDF	50 Pages

Scroll/Zoom	100%

制造商	AMCC [Applied Micro Circuits Corporation]

网页	http://www.amcc.com

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5 / 50 page

PPC405EP – PowerPC 405EP Embedded Processor

Revision 1.07 – September 10, 2007

AMCC

Data Sheet

Figure 1. PPC405EP Embedded Controller Functional Block Diagram

The PPC405EP is designed using the IBM Microelectronics Blue LogicTM methodology in which major functional

blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent

way to create complex ASICs using IBM CoreConnectTM Bus Architecture.

PPC405

Processor Core

DOCM

IOCM

DCU

ICU

OCM

Control

OCM

SRAM

DCR Bus

16KB

On-chip Peripheral Bus (OPB)

GPIO

IIC

GPT

UART

MAL

Ethernet

DMA

Bridge

Processor Local Bus (PLB)

SDRAM

PCI Bridge

External

Bus

Controller

Clock

Control

Reset

Power

Mgmt

JTAG

Trace

Timers

MMU

MII

Controller

OPB

Interrupt

Controller

Arb

29-bit addr

16-bit data

13-bit addr

32-bit data

Universal

I-Cache

D-Cache

(4-Channel)

66 MHz max (async)

DCRs

16KB

Arb

Event

Counters

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