PPC405EP – PowerPC 405EP Embedded Processor

Revision 1.07 – September 10, 2007

AMCC

43

Data Sheet

Table 13. Peripheral Interface Clock Timings

Parameter

Min

Max

Units

PCIClk input frequency (asynchronous mode)

Note 1

66.66

MHz

PCIClk period (asynchronous mode)

15

Note 1

ns

PCIClk input high time

40% of nominal period

60% of nominal period

ns

PCIClk input low time

40% of nominal period

60% of nominal period

ns

EMC0MDClk output frequency

–

2.5

MHz

EMC0MDClk period

400

–

ns

EMC0MDClk output high time

160

–

ns

EMC0MDClk output low time

160

–

ns

PHY0Tx0:1Clk input frequency

2.5

25

MHz

PHY0Tx0:1Clk period

40

400

ns

PHY0Tx0:1Clk input high time

35% of nominal period

–

ns

PHY0Tx0:1Clk input low time

35% of nominal period

–

ns

PHY0Rx0:1Clk input frequency

2.5

25

MHz

PHY0Rx0:1Clk period

40

400

ns

PHY0Rx0:1Clk input high time

35% of nominal period

–

ns

PHY0Rx0:1Clk input low time

35% of nominal period

–

ns

PerClk output frequency

–

66.66

MHz

PerClk period

15

–

ns

PerClk output high time

45% of nominal period

55% of nominal period

ns

PerClk output low time

45% of nominal period

55% of nominal period

ns

PerClk clock edge stability (phase jitter, cycle to cycle)

± 0.3

ns

Note:

1. In asynchronous PCI mode the minimum PCIClk frequency is 1/8 the PLB Clock. Refer to the PowerPC 405EP Embedded Processor

User’s Manual for more information.