PPC405EP – PowerPC 405EP Embedded Processor

Revision 1.07 – September 10, 2007

AMCC

7

Data Sheet

Table 2. DCR Address Map

Function

Start Address

End Address

Size

0x000

0x3FF

By function:

Reserved

0x000

0x00F

16W

Memory Controller Registers

0x010

0x011

2W

External Bus Controller Registers

0x012

0x013

2W

Reserved

0x014

0x017

2W

On-Chip Memory Controller Registers

0x018

0x01F

8W

Reserved

0x020

0x07F

96W

PLB Registers

0x080

0x08F

16W

Reserved

0x090

0x09F

16W

OPB Bridge Out Registers

0x0A0

0x0A7

8W

Reserved

0x0A8

0x0AF

6W

Clock, Control, and Reset

0x0B0

0x0B7

8W

Power Management

0x0B8

0x0BF

8W

Interrupt Controller

0x0C0

0x0CF

16W

Reserved

0x0D0

0x0FF

48W

DMA Controller Registers

0x100

0x13F

64W

Reserved

0x140

0x17F

64W

Ethernet MAL Registers

0x180

0x1FF

128W

Event Counters

0x200

0x203

4W

Reserved

0x204

0x3FF

508W

Notes:

1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit

(word) register, or 1 kiloword (KW) (which equals 4 KB).