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PPC405EP 数据表(PDF) 39 Page - Applied Micro Circuits Corporation |
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PPC405EP 数据表(HTML) 39 Page - Applied Micro Circuits Corporation |
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39 / 50 page ![]() PPC405EP – PowerPC 405EP Embedded Processor Revision 1.07 – September 10, 2007 AMCC 39 Data Sheet Table 11. DC Electrical Characteristics Parameter Symbol Minimum Typical Maximum Unit Active Operating Current (VDD)–266MHz IDD 300 610 mA Active Operating Current (VDD)–333MHz IDD 325 690 mA Active Operating Current (OVDD)IODD 45 200 mA PLL VDD Input current IPLL 16 23 mA Active Operating Power–266 MHz PDD 0.72 1.92 W Active Operating Power–333MHz PDD 0.76 2.07 W Note: 1. The maximum current and power values listed above are not guaranteed to be the highest obtainable. These values are dependent on many factors including the type of applications running, clock rates, use of internal functional capabilities, external interface usage, case temperature, and the power supply voltages. Your specific application can produce significantly different results. VDD (logic) current and power are primarily dependent on the applications running and the use of internal chip functions (DMA, PCI, Ethernet, and so on). OVDD (I/O) current and power are primarily dependent on the capacitive loading, frequency, and utilization of the external buses. The following information provides details about the conditions under which the values in the table above could be obtained: a. In general, there would be four PCI devices, an external bus master on the peripheral bus, and external wrap-back on the Ethernet port. For IODD measurements, PLB = 133.3MHz, OPB = PerClk = 66.6MHz, and PCI = SysClk = 33.3MHz. b. Typical current and power are characterized at VDD = +1.8V, OVDD = +3.3V, and TC = +36°C while running various applications under the Linux operating system. c. Maximum current and power are characterized at VDD = +1.9V, OVDD = +3.6V, and TC = +85°C while running applications designed to maximize CPU power consumption. An external PCI master heavily loads the PCI bus with transfers targeting SDRAM while the internal DMA controller further increases SDRAM bus traffic. 2. AVDD should be derived from VDD using the following circuit: VDD C1 C2 C3 AVDD L1 L1 – 2.2 μH SMT inductor (equivalent to MuRata LQH3C2R2M34) or SMT chip ferrite bead (equivalent to MuRata BLM31A700S) C1 – 3.3 μF SMT tantalum C2 – 0.1 μF SMT monolithic ceramic capacitor with X7R dielectric or equivalent C3 – 0.01 μF SMT monolithic ceramic capacitor with X7R dielectric or equivalent + AGND GND |
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