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PPC405EP 数据表(PDF) 34 Page - Applied Micro Circuits Corporation

部件名 PPC405EP
功能描述  PowerPC 405EP Embedded Processor
PDF  50 Pages
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制造商  AMCC [Applied Micro Circuits Corporation]
网页  http://www.amcc.com
标志 AMCC - Applied Micro Circuits Corporation

PPC405EP 数据表(HTML) 34 Page - Applied Micro Circuits Corporation

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PPC405EP – PowerPC 405EP Embedded Processor
34
AMCC
Revision 1.07 – September 10, 2007
Data Sheet
PerReady
Ready to transfer data.
I
5V tolerant
3.3V LVTTL
1
[PerBLast]
Used to indicates the last transfer of a memory access.
To access this function, software must toggle a DCR bit.
I/O
5V tolerant
3.3V LVTTL
1, 7
PerClk
Peripheral clock to be used by peripheral slaves.
O
5V tolerant
3.3V LVTTL
ExtReset
Peripheral reset to be used by peripheral slaves.
O
5V tolerant
3.3V LVTTL
Internal Peripheral Interface
UART0_Rx
UART0 Serial Data In.
I
5V tolerant
3.3V LVTTL
1
UART0_Tx
UART0 Serial Data Out.
O
5V tolerant
3.3V LVTTL
6
[UART0_DCD]
UART0 Data Carrier Detect.
To access this function, software must toggle a DCR bit.
I
5V tolerant
3.3V LVTTL
1
[UART0_DSR]
UART0 Data Set Ready.
To access this function, software must toggle a DCR bit.
I
5V tolerant
3.3V LVTTL
1
UART0_CTS
UART0 Clear To Send.
I
5V tolerant
3.3V LVTTL
1
[UART0_DTR]
UART0 Data Terminal Ready.
To access this function, software must toggle a DCR bit.
O
5V tolerant
3.3V LVTTL
UART0_RTS
UART0 Request To Send.
O
5V tolerant
3.3V LVTTL
6
[UART0_RI]
UART0 Ring Indicator.
To access this function, software must toggle a DCR bit.
I
5V tolerant
3.3V LVTTL
1
[UART1_Rx]
UART1 Serial Data In.
To access this function, software must toggle a DCR bit.
I
5V tolerant
3.3V LVTTL
1
[UART1_Tx]
UART1 Serial Data Out.
To access this function, software must toggle a DCR bit.
O
5V tolerant
3.3V LVTTL
IICSCL
IIC Serial Clock.
I/O
3.3V IIC
1, 2
IICSDA
IIC Serial Data.
I/O
3.3V IIC
1, 2
Interrupts Interface
[IRQ0:6]
Interrupt requests
To access this function, software must toggle a DCR bit.
I
5V tolerant
3.3V LVTTL
1
JTAG Interface
TDI
Test data in.
I
5V tolerant
3.3V LVTTL
1, 4
TMS
JTAG test mode select.
I
5V tolerant
3.3V LVTTL
1, 4
Table 6. Signal Functional Description (Sheet 4 of 6)
Secondary multiplexed signals are shown in brackets.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 30.
Signal Name
Description
I/O
Type
Notes



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