PPC405EP datasheet(33/50 Pages) AMCC

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PPC405EP – PowerPC 405EP Embedded Processor

Revision 1.07 – September 10, 2007

AMCC

Data Sheet

SDRAM Interface

MemData00:31

Memory data bus.

Notes:

1. MemData00 is the most significant bit (msb).

2. MemData31 is the least significant bit (lsb).

I/O

3.3V LVTTL

MemAddr12:00

Memory address bus.

Notes:

1. MemAddr12 is the most significant bit (msb).

2. MemAddr00 is the least significant bit (lsb).

3.3V LVTTL

BA1:0

Bank Address supporting up to 4 internal banks.

3.3V LVTTL

RAS

Row Address Strobe.

3.3V LVTTL

CAS

Column Address Strobe.

3.3V LVTTL

DQM0:3

DQM for byte lane: 0 (MemData00:7),

1 (MemData08:15),

2 (MemData16:23), and

3 (MemData24:31)

3.3V LVTTL

BankSel0:1

Select up to two external SDRAM banks.

3.3V LVTTL

Write Enable.

3.3V LVTTL

ClkEn0:1

SDRAM Clock Enable.

3.3V LVTTL

MemClkOut0:1

Two copies of an SDRAM clock allows, in some cases, glueless

SDRAM attach without requiring this signal to be repowered by a PLL

or zero-delay buffer.

3.3V LVTTL

External Slave Peripheral Interface

PerData00:15

Peripheral data bus.

Note: PerData00 is the most significant bit (msb) on this bus.

I/O

5V tolerant

3.3V LVTTL

PerAddr03:05

PerAddr06:31

Peripheral address bus.

Note: PerAddr03 is the most significant bit (msb) on this bus.

I/O

5V tolerant

3.3V LVTTL

PerWBE0:1

These pins act as byte-enables which are valid for an entire cycle or

as write-byte-enables which are valid for each byte on each data

transfer, allowing partial word transactions.

5V tolerant

3.3V LVTTL

[PerWE]

Peripheral write enable. Low when either of the two PerWBE0:1 write

byte enables are low.

To access this function, software must toggle a DCR bit.

5V tolerant

3.3V LVTTL

PerCS0

Peripheral chip select bank 0.

5V tolerant

3.3V LVTTL

[PerCS1:4]

Four additional peripheral chip selects

To access this function, software must toggle a DCR bit.

5V tolerant

3.3V LVTTL

1, 7

PerOE

Peripheral output enable.

5V tolerant

3.3V LVTTL

PerR/W

Peripheral read/write. High indicates a read from memory, low

indicates a write to memory.

5V tolerant

3.3V LVTTL

Table 6. Signal Functional Description (Sheet 3 of 6)

Secondary multiplexed signals are shown in brackets.

Notes:

1. Receiver input has hysteresis.

2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.

3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.

4. If not used, must pull up.

5. If not used, must pull down.

6. Strapping input during reset; pull up or pull down as required.

7. Pull-up may be required. See “External Bus Control Signals” on page 30.

Signal Name

Description

I/O

Type

Notes

PPC405EP 数据表(PDF) 33 Page - Applied Micro Circuits Corporation

PPC405EP 数据表(HTML) 33 Page - Applied Micro Circuits Corporation

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PPC405EP 数据表(PDF) 33 Page - Applied Micro Circuits Corporation

PPC405EP 数据表(HTML) 33 Page - Applied Micro Circuits Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

数据表 下载

链接网址

数据表下载