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PPC440EP 数据表(PDF) 48 Page - Applied Micro Circuits Corporation |
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PPC440EP 数据表(HTML) 48 Page - Applied Micro Circuits Corporation |
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48 / 84 page ![]() 48 AMCC Proprietary 440EP – PPC440EP Embedded Processor Revision 1.26 – April 25, 2007 Data Sheet Signal Descriptions The PPC440EP embedded controller is packaged in a 456-ball enhanced plastic ball grid array (E-PBGA). The following tables describe the package level pinout. In the table “Signal Functional Description” on page 50, each I/O signal is listed along with a short description of its function. Active-low signals (for example, RAS) are marked with an overline. Please see “Signals Listed Alphabetically” on page 17 for the pin (ball) number to which each signal is assigned. Multiplexed Signals Some signals are multiplexed on the same pin so that the pin can be used for different functions. In most cases, the signal names shown in this table are not accompanied by signal names that may be multiplexed on the same pin. If you need to know what, if any, signals are multiplexed with a particular signal, look up the name in “Signals Listed Alphabetically” on page 17. It is expected that in any single application a particular pin will always be programmed to serve the same function. The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible. The circuit type for multiplexed signals is shown as “Multiplex.” The actual circuit type is the same as the primary signal. Multipurpose Signals In addition to multiplexing, some pins are also multi-purpose. For example, the EBC peripheral controller address pins (PerAddr) are used as outputs by the PPC440EP to broadcast an address to external slave devices when the PPC440EP has control of the external bus. When during the course of normal chip operation an external master gains ownership of the external bus, these same pins are used as inputs which are driven by the external master and received by the EBC in the PPC440EP. In this example, the pins are also bidirectional, serving both as inputs and outputs. Table 5. Pin Summary Group No. of Pins Total Signal Pins 304 AVDD 1 SAVDD 1 SAGnd 1 AGnd 1 OVDD 18 SVDD 18 VDD 32 Gnd 80 Total Power Pins 152 Reserved 0 Total Pins 456 |
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