PPC440EP datasheet(73/84 Pages) AMCC

部件名	PPC440EP

功能描述	Power PC 440EP Embedded Processor

PDF	84 Pages

Scroll/Zoom	100%

制造商	AMCC [Applied Micro Circuits Corporation]

网页	http://www.amcc.com

标志

73 / 84 page

AMCC Proprietary

440EP – PPC440EP Embedded Processor

Data Sheet

Revision 1.26 – April 25, 2007

DDR SDRAM Write Operation

The following diagram illustrates the relationship among the signals involved with a DDR write operation.

Figure 8. DDR SDRAM Write Cycle Timing

DQS

MemData

PLB Clk

MemClkOut0

MemClkOut0(90)

Addr/Cmd

TSK

TSA

THA

TDS

TSD

THD

TSD

THD

TSA = Setup time for address and command signals to MemClkOut0(90)

TSK = Delay from rising edge of MemClkOut0(0) to rising/falling edge of signal (skew)

THA = Hold time for address and command signals from MemClkOut0(90)

TDS = Delay from rising/falling edge of clock to the rising/falling edge of DQS

TSD = Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)

THD = Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)

PPC440EP 数据表(PDF) 73 Page - Applied Micro Circuits Corporation