PPC440EP datasheet(79/84 Pages) AMCC

79 / 84 page

AMCC Proprietary

440EP – PPC440EP Embedded Processor

Data Sheet

Revision 1.26 – April 25, 2007

Example 3:

In this example, ECC is enabled. This requires that Stage 3 data be sampled at (3). If ECC is disabled, the system

will still work, but there will be more latency before the data is sampled into RDSP. In this example, TT and TTE are

system dependent and taken into account by controller initialization software.

Figure 13. DDR SDRAM Read Cycle Timing—Example 3

DQS at pin

PLB Clock

Read Clock Delayed

TSIN

Data at pin

DQS Stage 1 C

TDIN

Data in Stage 1 D

Data out Stage 1

High

Low

Data out Stage 3

High

Low

with ECC

TT = Propagation delay from Stage 2 input to RDSP input w/o ECC

Data out Stage 2

High

Low

Data out RDSP

High

Low

(3)

with ECC

Data in at RDSP

High

Low

with ECC

TTE = Propagation delay from Stage 2 input to RDSP input with ECC

TTE

PPC440EP 数据表(PDF) 79 Page - Applied Micro Circuits Corporation

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