PPC440EP datasheet(76/84 Pages) AMCC

76 / 84 page

AMCC Proprietary

440EP – PPC440EP Embedded Processor

Revision 1.26 – April 25, 2007

Data Sheet

Figure 10. DDR SDRAM Read Data Path

In the following examples, the data strobes (DQS) and the data are shown to be coincident. There is actually a

slight skew as specified by the SDRAM specifications, and there can be additional skew due to loading and signal

routing. It is recommended that the signal length for all of the eight DQS signals be matched.

Table 22. I/O Timing—DDR SDRAM TSIN and TDIN

Notes:

1. TSIN = Delay from DQS at package pin to C on Stage 1 FF.

2. TDIN = Delay from data at package pin to D on Stage 1 FF.

3. Clock speed for the values in the table is 133MHz.

4. The time values for TSIN include 1/4 of a cycle at 133MHz (7.5ns x 0.25 = 1.875 ns).

Signal Name

TSIN (ns)

minimum

TSIN (ns)

maximum

Signal Name

TDIN (ns)

minimum

TDIN (ns)

maximum

DQS0

2.74

3.70

MemData00:07

0.86

1.87

DQS1

2.75

3.69

MemData08:15

0.87

1.86

DQS2

2.74

3.69

MemData16:23

0.89

1.86

DQS3

2.76

3.69

MemData24:31

0.88

1.85

DQS8

2.77

3.68

ECC0:7

0.89

1.83

Stage 1

Stage 2

Stage 3

RDSP

PLB bus

FF,

Data

Read Select

(SDRAM0_TR1)

DQS

1/4

Cycle

Delay

PLB Clock

Programmed

Delay

Package pins

Mux

Read Clock

FF Timing:

TIS = Input setup time = 0.2ns

TIH = Input hold time = 0.1ns

TP = Propagation delay (D to Q or C to Q) = 0.4ns maximum

ECC

FF: Flip-Flop

XL: Transparent Latch

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