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PPC440EP 数据表(PDF) 80 Page - Applied Micro Circuits Corporation |
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PPC440EP 数据表(HTML) 80 Page - Applied Micro Circuits Corporation |
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80 / 84 page ![]() 80 AMCC Proprietary 440EP – PPC440EP Embedded Processor Revision 1.26 – April 25, 2007 Data Sheet Initialization The PPC440EP provides the option for setting initial parameters based on default values or by reading them from a slave PROM attached to the IIC0 bus (see “EEPROM” below). Some of the default values can be altered by strapping on external pins (see “Strapping” below). Strapping While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable certain default initial conditions prior to PPC440EP start-up. The actual capture instant is the nearest reference clock edge before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0) resistors to select the desired default conditions. These pins are used for strap functions only during reset. Following reset they are used for normal functions. The signal names assigned to the pins for normal operation are shown in parentheses following the pin number. The following table lists the strapping pins along with their functions and strapping options: EEPROM During reset, initial conditions other than those obtained from the strapping pins can be read from a ROM device connected to the IIC0 port. At the de-assertion of reset, if the bootstrap controller is enabled, the PPC440EP sequentially reads 16 bytes from the ROM device on the IIC0 port and sets the SDR0_SDSTP0, SDR0_SDSTP1, SDR0_SDSTP2 and SDR0_SDSTP3 registers accordingly. The initialization settings and their default values are covered in detail in the PowerPC 440EP User’s Manual. Table 23. Strapping Pin Assignments Function Option Ball Strapping R25 (UART0_DCD) U26 (UART0_DSR) V26 (UART0_CTS) Serial device is disabled. Each of the six options (A– F) is a combination of boot source, boot-source width, and clock frequency specifications. Refer to the IIC Bootstrap Controller chapter in the PPC440EP Embedded Processor User’s Manual for details. A 000 B 001 C 010 D 011 E 100 F 110 Serial device is enabled. The option being selected is the IIC0 slave address that will respond with configuration data. Note: If reading of configuration data from the serial device fails, the PPC440EP defaults to configuration X. G (0xA8) 101 H (0xA4) 111 |
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