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PPC440EP 数据表(PDF) 5 Page - Applied Micro Circuits Corporation |
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PPC440EP 数据表(HTML) 5 Page - Applied Micro Circuits Corporation |
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5 / 84 page  AMCC Proprietary 5 440EP – PPC440EP Embedded Processor Data Sheet Revision 1.26 – April 25, 2007 Block Diagram Figure 2. PPC440EP Functional Block Diagram The PPC440EP is a system on a chip (SOC) using IBM CoreConnect Bus™ Architecture. Processor Core DCR Bus 32KB On-chip Peripheral Bus (OPB 0) GPIO IIC UART PLB (PLB4—128 bits) DDR SDRAM External Peripheral Controller Controller Clock Control Reset Power Mgmt JTAG Trace Timers MMU - 30-bit addr - 16-bit data - 13-bit addr - 32-bit data NAND Flash Controller UIC I-Cache 32KB D-Cache PPC440 PCI Bridge x2 x4 MAL Ethernet x2 DCRs GPT 1 MII or 2 RMII or 2 SMII ZMII 66MHz max 10/100 66MHz max 266MHz max PLB (PLB3—64 bits) PLB Bridge SPI USB 2.0 - 32 bits - 6 devices Performance Monitor FPU External DMA Controller OPB Bridge BSC 10 UTMI DMA Controller OPB Bridge 1.1PHY D+/D − OPB 1 USB 1.1 Host 1.1PHY Device D+/D − Interrupts |
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