TMP86FS28DFG datasheet(44/272 Pages) TOSHIBA

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2. Operational Description

2.3 Reset Circuit

TMP86FS28DFG

2.3.2 Address trap reset

If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction

from the on-chip RAM (when WDTCR1<ATAS> is set to “1”), DBR or the SFR area, address trap reset will be

generated. The reset time is maximum 24/fc[s] (1.5

µs at 16.0 MHz).

Note:The operating mode under address trapped is alternative of reset or interrupt. The address trap area is alter-

native.

Note 1: Address “a” is in the SFR, DBR or on-chip RAM (WDTCR1<ATAS> = “1”) space.

Note 2: During reset release, reset vector “r” is read out, and an instruction at address “r” is fetched and decoded.

Figure 2-16 Address Trap Reset

2.3.3 Watchdog timer reset

Refer to Section “Watchdog Timer”.

2.3.4 System clock reset

If the condition as follows is detected, the system clock reset occurs automatically to prevent dead lock of the

CPU. (The oscillation is continued without stopping.)

- In case of clearing SYSCR2<XEN> and SYSCR2<XTEN> simultaneously to “0”.

- In case of clearing SYSCR2<XEN> to “0”, when the SYSCR2<SYSCK> is “0”.

- In case of clearing SYSCR2<XTEN> to “0”, when the SYSCR2<SYSCK> is “1”.

The reset time is maximum 24/fc (1.5

µs at 16.0 MHz).

Instruction at address r

16/fc [s]

maximum 24/fc [s]

Instruction

execution

Internal reset

JP a

Reset release

Address trap is occurred

4/fc to 12/fc [s]

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