TMP86FS28DFG datasheet(75/272 Pages) TOSHIBA

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Page 63

TMP86FS28DFG

5.6 Port P5 (P50 to P57)

Port P5 is an 8-bit input/output port that can also be used for timer/counter input/output, LCD segment output, or

UART input/output.

A reset initializes the output latch (P5DR) to “1”, the Pch control (P5OUTCR) to “0”, and the LCD output control

To use a pin in Port P5 as an input port, timer/counter input, or UART input, set P5DR to “1” and then set the cor-

responding bit in P5LCR and P5OUTCR to “0”.

To use a pin in Port P5 as an LCD segment output, set the corresponding bit in P5LCR to “1”.

To use a pin in Port P5 as a UART output or timer/counter output, set P5DR to "1" and then set the corresponding

bit in P5LCR to “0”.

The output circuit of Port P5 can be set either as sink open-drain output (“0”) or CMOS otuput (“1”) individually

for each bit in P5OUTCR.

Port P5 has a separate data input register. The output latch state can be read from the P5DR register, and the pin

state can be read from the P5PRD register.

Note: An asterisk (*) indicates that either “1” or “0” can be set.

Figure 5-7 Port P5

Table 5-8 Register Programming for Port P5 (P50 to P57)

Function

Programmed Value

P5DR

P5OUTCR

P5LCR

Port input, UART input, timer/counter input

“1”

“0”

Port “0” output

“0”

Set as

appropriate.

“0”

Port “1” output, UART output

“1”

“0”

LCD segment output

“1”

Data input (P5PRD)

Output latch read (P5DR)

STOP

OUTEN

P5OUTCRi input

Data output (P5DR)

P5OUTCRi

P5i

Note) i = 7~0

LCD data output

P5LCRi

P5LCRi input

Control output

Control input

Output latch

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