TMP86FS28DFG datasheet(70/272 Pages) TOSHIBA

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Page 58

5. I/O Ports

5.3 Port P2 (P20 to P22)

TMP86FS28DFG

5.3 Port P2 (P20 to P22)

Port P2 is a 3-bit input/output port that can also be used for external interrupt input, STOP mode release signal

input, or low-frequency resonator connection.

To use Port P2 as an input port or function pins, set the output latch (P2DR) to “1”. A reset initializes P2DR to “1”.

In the dual clock mode, pins P21 (XTIN) and P22 (XOUT) are connected with a low-frequency resonator (32.768

kHz). In the single clock mode, pins P21 and P22 can be used as normal input/output port pins.

It is recommended that pin P20 be used as an external interrupt input, STOP release signal input, or input port.

(When P20 is used as an output port, the interrupt latch is set on the falling edge of the output pulse.)

Port P2 has a separate data input register. The output latch state can be read from the P2DR register, and the pin

state can be read from the P2PRD register.

When a read instruction is executed on P2DR or P2PRD, bits 7 to 3 are read as undefined.

Figure 5-4 Port P2

Note: Since pin P20 is also used as a STOP pin, the output of P20 becomes high-impedance in STOP mode regardless of the

OUTEN state.

P2DR

(0002H)

R/W

543

P22

XTOUT

P21

XTIN

P20

INT5

STOP

(Initial value: **** *111)

P2PRD

(0FF2H)

Read only

543

P22

P21

P20

Data input (P20PRD)

Output latch read (P21)

Data output (P21)

Data output (P20)

Data input (P20)

Data input (P21PRD)

Output latch read (P22)

Data input (P22PRD)

Data output (P22)

STOP

OUTEN

XTEN

P22 (XTOUT)

P21 (XTIN)

P20 (INT5, STOP)

Control input

Output latch

Osc. enable

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