TMP86FS28DFG datasheet(96/272 Pages) TOSHIBA

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Page 84

8. 16-Bit TimerCounter (TC10,TC11)

8.1 16-Bit TimerCounter 10

TMP86FS28DFG

8.1.2 TimerCounter Control

The TimerCounter 10 is controlled by the TimerCounter 10 control register (TC10CR) and two 16-bit timer

registers (TC10DRA and TC10DRB).

Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz]

Note 2: The timer register consists of two shift registers. A value set in the timer register becomes valid at the rising edge of the

first source clock pulse that occurs after the upper byte (TC10DRAH and TC10DRBH) is written. Therefore, write the

lower byte and the upper byte in this order (it is recommended to write the register with a 16-bit access instruction). Writing

only the lower byte (TC10DRAL and TC10DRBL) does not enable the setting of the timer register.

Note 3: To set the mode, source clock, PPG output control and timer F/F control, write to TC10CR1 during TC10S=00. Set the

timer F/F10 control until the first timer start after setting the PPG mode.

Timer Register

98765

43210

TC10DRA

(0011H, 0010H)

TC10DRAH (0011H)

TC10DRAL (0010H)

(Initial value: 1111 1111 1111 1111)

Read/Write

TC10DRB

(0013H, 0012H)

TC10DRBH (0013H)

TC10DRBL (0012H)

(Initial value: 1111 1111 1111 1111)

Read/Write (Write enabled only in the PPG output mode)

TimerCounter 10 Control Register

TC10CR

(0014H)

432

TFF10

ACAP10

MCAP10

METT10

MPPG10

TC10S

TC10CK

TC10M

Read/Write

(Initial value: 0000 0000)

TFF10

Timer F/F10 control

0: Clear

1: Set

R/W

ACAP10

Auto capture control

0:Auto-capture disable

1:Auto-capture enable

R/W

MCAP10

Pulse width measure-

ment mode control

0:Double edge capture

1:Single edge capture

METT10

External trigger timer

mode control

0:Trigger start

1:Trigger start and stop

MPPG10

PPG output control

0:Continuous pulse generation

1:One-shot

TC10S

TC10 start control

Timer

Extrig-

ger

Event

Win-

dow

Pulse

PPG

R/W

00: Stop and counter clear

OOOOOO

01: Command start

––––

10: Rising edge start

(Ex-trigger/Pulse/PPG)

Rising edge count (Event)

Positive logic count (Window)

–

OOOOO

11: Falling edge start

(Ex-trigger/Pulse/PPG)

Falling edge count (Event)

Negative logic count (Window)

–

OOOOO

TC10CK

TC10 source clock select

[Hz]

NORMAL1/2, IDLE1/2 mode

Divider

SLOW,

SLEEP

mode

R/W

DV7CK = 0

DV7CK = 1

fc/211

fs/23

DV9

fs/23

fc/27

DV5

–

fc/23

DV1

–

External clock (TC10 pin input)

TC10M

TC10 operating mode

select

00: Timer/external trigger timer/event counter mode

01: Window mode

10: Pulse width measurement mode

11: PPG (Programmable pulse generate) output mode

R/W

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