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TMP86FS28DFG 数据表(PDF) 64 Page - Toshiba Semiconductor |
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TMP86FS28DFG 数据表(HTML) 64 Page - Toshiba Semiconductor |
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64 / 272 page  Page 52 5. I/O Ports TMP86FS28DFG Each output port contains a latch for holding output data. All input ports do not have latches, making it necessary to externally hold input data until it is read externally or to read input data multiple times before it is processed. Fig- ure 5-1 shows input/output timings. External data is read from an input/output port in the S1 state of the read cycle in instruction execution. Since this timing cannot be recognized externally, transient input such as chattering must be processed by software. Data is out- put to an input/output port in the S2 state of the write cycle in instruction execution. Note: The positions of the read and write cycles may vary depending on the instruction. Figure 5-1 Input/Output Timings (Example) Instruction execution cycle Input strobe Data input Ex: LD A, (x) Fetch cycle Fetch cycle Read cycle S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3 Instruction execution cycle Output latch pulse Data output Ex: LD (x), A Fetch cycle Fetch cycle Write cycle S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3 (a) Input timing (b) Output timing |
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