TMP86FS28DFG datasheet(48/272 Pages) TOSHIBA

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Page 36

3. Interrupt Control Circuit

3.1 Interrupt latches (IL29 to IL2)

TMP86FS28DFG

3.1 Interrupt latches (IL29 to IL2)

An interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the unde-

fined instruction interrupt. When interrupt request is generated, the latch is set to “1”, and the CPU is requested to

accept the interrupt if its interrupt is enabled. The interrupt latch is cleared to "0" immediately after accepting inter-

rupt. All interrupt latches are initialized to “0” during reset.

The interrupt latches are located on address 002EH, 002FH, 003CH and 003DH in SFR area. Each latch can be

cleared to "0" individually by instruction. However, IL2 and IL3 should not be cleared to "0" by software. For clear-

ing the interrupt latch, load instruction should be used and then IL2 and IL3 should be set to "1". If the read-modify-

write instructions such as bit manipulation or operation instructions are used, interrupt request would be cleared

inadequately if interrupt is requested while such instructions are executed.

Interrupt latches are not set to “1” by an instruction.

Since interrupt latches can be read, the status for interrupt requests can be monitored by software.

Note: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to

"0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL

(Enable interrupt by EI instruction)

In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on

interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL

should be executed before setting IMF="1".

3.2 Interrupt enable register (EIR)

The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the non-maskable

interrupts (Software interrupt, undefined instruction interrupt, address trap interrupt and watchdog interrupt). Non-

maskable interrupt is accepted regardless of the contents of the EIR.

The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). These

registers are located on address 002CH, 002DH, 003AH and 003BH in SFR area, and they can be read and written

by an instructions (Including read-modify-write instructions such as bit manipulation or operation instructions).

3.2.1 Interrupt master enable flag (IMF)

The interrupt enable register (IMF) enables and disables the acceptance of the whole maskable interrupt.

While IMF = “0”, all maskable interrupts are not accepted regardless of the status on each individual interrupt

enable flag (EF). By setting IMF to “1”, the interrupt becomes acceptable if the individuals are enabled. When

an interrupt is accepted, IMF is cleared to “0” after the latest status on IMF is stacked. Thus the maskable inter-

rupts which follow are disabled. By executing return interrupt instruction [RETI/RETN], the stacked data,

which was the status before interrupt acceptance, is loaded on IMF again.

The IMF is located on bit0 in EIRL (Address: 003AH in SFR), and can be read and written by an instruction.

The IMF is normally set and cleared by [EI] and [DI] instruction respectively. During reset, the IMF is initial-

ized to “0”.

Example 1 :Clears interrupt latches

; IMF

← 0

LDW

(ILL), 1110100000111111B

; IL12, IL10 to IL6

← 0

; IMF

← 1

Example 2 :Reads interrupt latchess

WA, (ILL)

; W

← ILH, A ← ILL

Example 3 :Tests interrupt latches

TEST

(ILL). 7

; if IL7 = 1 then jump

F, SSET

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