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TMP86FS28DFG 数据表(PDF) 47 Page - Toshiba Semiconductor |
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TMP86FS28DFG 数据表(HTML) 47 Page - Toshiba Semiconductor |
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47 / 272 page  Page 35 TMP86FS28DFG 3. Interrupt Control Circuit The TMP86FS28DFG has a total of 23 interrupt sources excluding reset. Interrupts can be nested with priorities. Four of the internal interrupt sources are non-maskable while the rest are maskable. Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors. The interrupt latch is set to “1” by the generation of its interrupt request which requests the CPU to accept its inter- rupts. Interrupts are enabled or disabled by software using the interrupt master enable flag (IMF) and interrupt enable flag (EF). If more than one interrupts are generated simultaneously, interrupts are accepted in order which is domi- nated by hardware. However, there are no prioritized interrupt factors among non-maskable interrupts. Note 1: To use the address trap interrupt (INTATRAP), clear WDTCR1<ATOUT> to “0” (It is set for the “reset request” after reset is cancelled). For details, see “Address Trap”. Note 2: To use the watchdog timer interrupt (INTWDT), clear WDTCR1<WDTOUT> to "0" (It is set for the "Reset request" after reset is released). For details, see "Watchdog Timer". Interrupt Factors Enable Condition Interrupt Latch Vector Address Priority Internal/External (Reset) Non-maskable – FFFE 1 Internal INTSWI (Software interrupt) Non-maskable – FFFC 2 Internal INTUNDEF (Executed the undefined instruction interrupt) Non-maskable – FFFC 2 Internal INTATRAP (Address trap interrupt) Non-maskable IL2 FFFA 2 Internal INTWDT (Watchdog timer interrupt) Non-maskable IL3 FFF8 2 External INT0 IMF• EF4 = 1, INT0EN = 1 IL4 FFF6 5 External INT1 IMF• EF5 = 1 IL5 FFF4 6 Internal INTTBT IMF• EF6 = 1 IL6 FFF2 7 Internal INTTC10 IMF• EF7 = 1 IL7 FFF0 8 Internal INTRXD0 IMF• EF8 = 1 IL8 FFEE 9 Internal INTTXD0 IMF• EF9 = 1 IL9 FFEC 10 Internal INTTC11 IMF• EF10 = 1 IL10 FFEA 11 External INT2 IMF• EF11 = 1 IL11 FFE8 12 - Reserved IMF• EF12 = 1 IL12 FFE6 13 Internal INTSIO IMF• EF13 = 1 IL13 FFE4 14 - Reserved IMF• EF14 = 1 IL14 FFE2 15 - Reserved IMF• EF15 = 1 IL15 FFE0 16 - Reserved IMF• EF16 = 1 IL16 FFBE 17 - Reserved IMF• EF17 = 1 IL17 FFBC 18 - Reserved IMF• EF18 = 1 IL18 FFBA 19 - Reserved IMF• EF19 = 1 IL19 FFB8 20 Internal INTTC3 IMF• EF20 = 1 IL20 FFB6 21 Internal INTTC4 IMF• EF21 = 1 IL21 FFB4 22 External INT3 IMF• EF22 = 1 IL22 FFB2 23 Internal INTTC5 IMF• EF23 = 1 IL23 FFB0 24 Internal INTTC6 IMF• EF24 = 1 IL24 FFAE 25 External INT4 IMF• EF25 = 1 IL25 FFAC 26 External INT5 IMF• EF26 = 1 IL26 FFAA 27 Internal INTRXD1 IMF• EF27 = 1 IL27 FFA8 28 Internal INTTXD1 IMF• EF28 = 1 IL28 FFA6 29 Internal INTADC IMF• EF29 = 1 IL29 FFA4 30 - Reserved IMF• EF30 = 1 IL30 FFA2 31 - Reserved IMF• EF31 = 1 IL31 FFA0 32 |
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