AD4056BCPZ-R2 datasheet(41/67 Pages) AD

41 / 67 page

Data Sheet

AD4050/AD4056

SERIAL INTERFACE

analog.com

Rev. A | 41 of 67

The AD4050/AD4056 include optional error checking for register

reads and writes based on CRC-8, using the following polynomial:

x8+x2+x+1

(6)

The CRC is enabled by setting the CRC_EN and CRC_EN_B bit

fields to 0x1 and 0x2, respectively. When the CRC is enabled,

an 8-bit checksum code is appended to each register data byte,

as shown in Figure 63. The value of the checksum is calculated

from the data read or written over the SPI, which allows the

AD4050/AD4056 and the digital host to detect corrupted serial

communications.

When the AD4050/AD4056 receive a checksum that is inconsistent

with its corresponding SPI transaction, the transaction is considered

invalid, and the SPI_CRC_ERR bit in the INTERFACE_STATUS

(R/W1C). When the CRC is enabled, it is recommended to check

the SPI_CRC_ERR bit after each register read and write attempt.

When a register write has an invalid CRC, the contents of the

shown in Figure 63, the AD4050/AD4056 also ignore data for

registers following the invalid CRC. When a register read has an

invalid CRC, the digital host must discard the received data and

retry the register read.

The CRC-8 calculation is seeded by a nonzero value to detect if the

data lines are stuck low. The seed for the first CRC following each

CS falling edge is 0xA5. When performing bulk reads or writes, the

seed for all subsequent CRCs is the least significant byte (LSByte)

of the current register address. Table 18 summarizes the data and

seed values for all possible register read and write transactions in

configuration mode.

Table 18. CRC Data and Seed Values for Configuration Mode SPI Transactions

SPI Transaction Type

First CRC

Subsequent CRCs

Write

SDI

Seed = 0xA5, Data = [instruction phase data, register write

data]

Seed = LSByte of register address, Data = register write data

SDO

Seed = 0xA5, Data = [instruction phase data, register write

data]

Seed = LSByte of register address, Data = register write data

Read

SDI

Seed = 0xA5, Data = [instruction phase data, padding]

Not applicable

SDO

Seed = 0xA5, Data = [instruction phase data, register read

data]

Seed = LSByte of register address, Data = register read data

AD4056BCPZ-R2 数据表(PDF) 41 Page - Analog Devices

AD4056BCPZ-R2 数据表(HTML) 41 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

数据表下载

链接网址

AD4056BCPZ-R2 数据表(PDF) 41 Page - Analog Devices

AD4056BCPZ-R2 数据表(HTML) 41 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

数据表 下载

链接网址

数据表下载