AD4056BCPZ-R2 datasheet(1/67 Pages) AD

部件名	AD4056BCPZ-R2

功能描述	Compact, Low Power, 12-Bit, 2 MSPS/500 kSPS Easy Drive SAR ADC

PDF	67 Pages

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制造商	AD [Analog Devices]

网页	http://www.analog.com

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Data Sheet

AD4050/AD4056

Compact, Low Power, 12-Bit, 2 MSPS/500 kSPS Easy Drive SAR ADC

Rev. A

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FEATURES

►

Small footprint, big performance

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INL: ±0.1 LSB maximum

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SNR: 73.8 dB with VREF = 3.3 V

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1.35 nJ per conversion

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1.35 mW/0.68 mW at 1 MSPS/500 kSPS in sample mode

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370 μW/112 μW at 1 MSPS/300 kSPS in autonomous modes

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4.1 μW standby power

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Versatile signal conditioning integration

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Easy Drive features enable small, low-power AFE designs

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Compatible with differential and single-ended signal chains

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Wide common-mode input range

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Minimizes digital host activity and power dissipation

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Autonomous sampling with window comparator and interrupt

generation

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Averaging filter with continuous and burst sampling options

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Power cycling synchronization for companion devices

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4-wire SPI compatible with 1.8 V to 3.3 V logic

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2.00 mm × 2.6 mm LFCSP and 1.67 mm × 1.97 mm WLCSP

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Wide operating temperature range: −40°C to +125°C

APPLICATIONS

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Battery-powered data acquisition

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Vital signs monitoring

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Biological and chemical analysis

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Geologic and seismic sensing

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Motion and robotics

GENERAL DESCRIPTION

The AD4050/AD4056 are versatile, 12-bit, successive approxima-

tion register (SAR) analog-to-digital converters (ADCs) that enable

low-power, high-density data acquisition solutions without sacrific-

ing precision. These ADCs offer a unique balance of perform-

ance and power efficiency, plus innovative features for seamlessly

switching between high-resolution and low-power modes tailored to

the immediate needs of the system. The AD4050/AD4056 are ideal

for battery-powered, compact data acquisition and edge sensing

applications.

The Easy Drive features enable highly efficient analog front end

(AFE) designs. The small sampling capacitors (3.4 pF) maximize in-

put impedance, thus reducing the dependence on high-bandwidth,

power-hungry amplifiers typically required by SAR ADCs. The wide

input common-mode range grants inherent support for both differ-

ential and single-ended signals.

The AD4050/AD4056 support microcontrollers with power-down

modes and interrupt-driven firmware. The autonomous modes en-

able out-of-range event detection while the digital host sleeps.

The averaging modes deliver on-demand, high-resolution measure-

ments while offloading computations from the host processor. The

self timed device enable signal (DEV_EN) synchronizes AFE de-

vice power cycling to the ADC sampling instant, optimizing system

power consumption while minimizing power-up settling error arti-

facts. The AD4050/AD4056 also support power cycling the voltage

reference and using the supply as the ADC reference voltage

(VREF) for additional power savings.

The device configuration and ADC data readback are supported

via a robust, 4-wire serial peripheral interface (SPI) with cyclic

redundancy check (CRC) supported for all data transfers. The

AD4050/AD4056 are available in compact LFCSP and WLCSP

packages and operate across a wide temperature range, making

them ideal for a diverse set of applications.

FUNCTIONAL BLOCK DIAGRAM

Figure 1. Functional Block Diagram

类似零件编号 - AD4056BCPZ-R2

制造商	部件名	数据表	功能描述
Analog Devices	AD4056BCPZ-RL7	2Mb / 65P	Compact, Low Power, 12-Bit, 2 MSPS/500 kSPS Easy Drive SAR ADC Rev. 0

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类似说明 - AD4056BCPZ-R2

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Analog Devices	AD7482BSTZ	527Kb / 20P	3 MSPS, 12-Bit SAR ADC REV. B
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