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AD4056BCPZ-R2 数据表(PDF) 61 Page - Analog Devices

部件名 AD4056BCPZ-R2
功能描述  Compact, Low Power, 12-Bit, 2 MSPS/500 kSPS Easy Drive SAR ADC
PDF  67 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD4056BCPZ-R2 数据表(HTML) 61 Page - Analog Devices

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Data Sheet
AD4050/AD4056
REGISTER DETAILS
analog.com
Rev. A | 61 of 67
NOTE - The CHOP signal and the DEV_EN signal cannot be enabled at the same time.
INTERRUPT CONFIGURATION REGISTER
Address: 0x25, Reset: 0x21, Name: INTR_CONFIG
Table 42. Bit Descriptions for INTR_CONFIG
Bits
Bit Name
Description
Reset
Access
[7:6]
RESERVED
Reserved.
0x0
R
[5:4]
GP1_INTR_EN
GP1 Interrupt Configuration. Selects which of the threshold detection interrupt signals are passed through to the
GP1_INTR output signal.
0x2
R/W
0x0: Neither Interrupt.
0x1: MIN_INTR.
0x2: MAX_INTR.
0x3: Either Interrupt. GP1 outputs the logical OR of MAX_INTR and MIN_INTR signals.
[3:2]
RESERVED
Reserved.
0x0
R
[1:0]
GP0_INTR_EN
GP0 Interrupt Configuration. Selects which of the threshold detection interrupt signals are passed through to the
GP0_INTR output signal.
0x1
R/W
0x0: Neither Interrupt.
0x1: MIN_INTR. Default.
0x2: MAX_INTR.
0x3: Either Interrupt. GP0 outputs the logical OR of MAX_INTR and MIN_INTR signals.
CHOP SIGNAL CONFIGURATION REGISTER
Address: 0x26, Reset: 0x00, Name: CHOP_CONFIG
Chop Window Length
0xB: 2048.
0xA: 1024.
0x9: 512.
...
0x2: 4.
0x1: 2.
0x0: 1.
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:4] RESERVED
[3:0] CHOP_WIN_LEN (R/W)
Table 43. Bit Descriptions for CHOP_CONFIG
Bits
Bit Name
Description
Reset
Access
[7:4]
RESERVED
Reserved.
0x0
R
[3:0]
CHOP_WIN_LEN
Chop Window Length. Sets the number of ADC samples taken before switching the CHOP signal state. Set
CHOP_WIN_LEN to implement the desired ratio of the CHOP signal period and ADC sampling period.
0x0
R/W
0x0: 1.
0x1: 2.
0x2: 4.
0x3: 8.
0x4: 16.
0x5: 32.
0x6: 64.



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