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AD4056BCPZ-R2 数据表(PDF) 20 Page - Analog Devices

部件名 AD4056BCPZ-R2
功能描述  Compact, Low Power, 12-Bit, 2 MSPS/500 kSPS Easy Drive SAR ADC
PDF  67 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD4056BCPZ-R2 数据表(HTML) 20 Page - Analog Devices

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Data Sheet
AD4050/AD4056
THEORY OF OPERATION
analog.com
Rev. A | 20 of 67
The AD4050/AD4056 serial interface outputs the ADC data into
multiples of bytes to maximize compatibility with microcontroller
direct memory access (DMA) controllers. The ADC Mode Output
Data Format section describes the serial interface data packet
format for each of the AD4050/AD4056 operating modes.
As described in the Wide Input Common-Mode Range section,
the AD4050/AD4056 support arbitrary input common-mode voltag-
es, therefore the devices inherently support both differential and
single-ended type signals. The AD4050/AD4056 support both twos
complement (signed) and straight binary (unsigned) formats to map
either differential signals or single-ended signals to the full 12-bit
ADC transfer function. The DATA_FORMAT bit in the ADC_MODES
register selects between the differential mode and single-ended
mode transfer functions as seen in Table 11 and Table 12.
Figure 34. ADC Ideal Transfer Function
Table 11. ADC Input Voltage to Output Code Mapping (Sample Mode)
Description
Differential Mode
Single-Ended Mode
VIN
Digital Output Code
VIN
Digital Output Code
FSR − 1 LSB
(2047/2048) × VREF
0x7FF
(4095/4096) × VREF
0xFFF
...
...
...
...
...
Midscale + 1 LSB
(1/2048) × VREF
0x001
(2049/4096) × VREF
0x801
Midscale
0 V
0x000
(½) × VREF
0x800
Midscale − 1 LSB
−(1/2048) × VREF
0xFFF
(2047/4096) × VREF
0x7FF
...
…
...
...
...
−FSR + 1 LSB
(−2047/2048) × VREF
0x801
(1/2048) × VREF
0x001
−FSR
−VREF
0x800
0 V
0x000
Table 12. ADC Input Voltage to Output Code Mapping (Averaging and Burst Averaging Modes)
Description
Differential Mode
Single-Ended Mode
VIN
Digital Output Code
VIN
Digital Output Code
FSR − 1 LSB
(8191/8192) × VREF
0x1FFF
(16383/16384) × VREF
0x3FFF
...
...
...
...
Midscale + 1 LSB
(1/8192) × VREF
0x0001
(8193/16384) × VREF
0x2001
Midscale
0 V
0x0000
(½) × VREF
0x2000
Midscale − 1 LSB
(−1/8192) × VREF
0xFFFF
(8191/16384) × VREF
0x1FFF
...
…
...
...
...
−FSR + 1 LSB
(−8191/8192) × VREF
0x2001
(1/16384) × VREF
0x0001
−FSR
−VREF
0x2000
0 V
0x0000



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