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AD4056BCPZ-R2 数据表(PDF) 57 Page - Analog Devices

部件名 AD4056BCPZ-R2
功能描述  Compact, Low Power, 12-Bit, 2 MSPS/500 kSPS Easy Drive SAR ADC
PDF  67 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD4056BCPZ-R2 数据表(HTML) 57 Page - Analog Devices

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Data Sheet
AD4050/AD4056
REGISTER DETAILS
analog.com
Rev. A | 57 of 67
RESERVED REGISTERS
Address: 0x0E, Reset: 0x00, Name: STREAM_MODE
Table 33. Bit Descriptions for STREAM_MODE
Bits
Bit Name
Description
Reset
Access
[7:0]
LOOP_COUNT
Reserved. This bit field must be set to 0x00.
0x0
R/W
Address: 0x0F, Reset: 0x00, Name: TRANSFER_CONFIG
Table 34. Bit Descriptions for TRANSFER_CONFIG
Bits
Bit Name
Description
Reset
Access
[7:3]
RESERVED
Reserved.
0x0
R
2
KEEP_STREAM_LENGTH_VAL
Reserved. This bit must be set to 0.
0x0
R/W
[1:0]
RESERVED
Reserved.
0x0
R
INTERFACE CONFIGURATION C REGISTER
Address: 0x10, Reset: 0x13, Name: INTERFACE_CONFIG_C
Additional interface configuration settings.
Table 35. Bit Descriptions for INTERFACE_CONFIG_C
Bits
Bit Name
Description
Reset
Access
[7:6]
CRC_EN
CRC Enable. Set CRC_EN to 0x1 and CRC_EN_B to 0x2 in the same register write to enable
interface CRC.
0x0
R/W
0: CRC Disabled.
1: CRC Enabled. Enables CRC if CRC_EN_B = 0x2.
5
STRICT_REGISTER_ACCESS
Reserved. This bit must be set to 0.
0x0
R/W
4
SEND_STATUS
Reserved. This bit must be set to 1.
0x1
R/W
[3:2]
RESERVED
Reserved.
0x0
R
[1:0]
CRC_EN_B
Inverted CRC Enable. To enable CRC, write as the inverted value of CRC_ENABLE.
0x3
R/W
INTERFACE STATUS REGISTER
Address: 0x11, Reset: 0x00, Name: INTERFACE_STATUS
Status bits indicating errors in register reads and/or writes in configuration mode. The interface status bits are active high and are cleared by
writing a 1 to their corresponding bit locations.



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