AD4056BCPZ-R2 datasheet(52/67 Pages) AD

52 / 67 page

Data Sheet

AD4050/AD4056

APPLICATIONS INFORMATION

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Rev. A | 52 of 67

Table 21. Serial Interface Output Data Rate Examples

VIO Range

Example fSCLK1

NBITS

fODR_MAX

VIO ≥ 3 V

62.5 MHz

1.69 MSPS

1.39 MSPS

1.18 MSPS

1.02 MSPS

3 V > VIO ≥1.7 V

33.3 MHz

1.22 MSPS

947 kSPS

772 kSPS

650 kSPS

1 The example fSCLK in this table correspond to tSCLK = 2 × tDSDO, where tDSDO is

the maximum data valid delay given in Table 5 and Table 6.

LAYOUT RECOMMENDATIONS

The following PCB layout guidelines are recommended to maximize

performance using the AD4050/AD4056:

►

Include a solid ground plane in the PCB layer underneath the

AD4050/AD4056. Ensure there are low-impedance connections

between the AD4050/AD4056 GND pins and the ground plane

layer.

►

Ensure the analog input and REF traces are physically separat-

ed from the digital interface traces to minimize crosstalk from

digital signal edges. Include a GND fill between the analog

and digital traces. Avoid routing the digital interface traces under-

neath the AD4050/AD4056 or the analog signal traces without

including a solid ground plane layer in between.

►

Ensure the impedance between the voltage reference circuitry

and the AD4050/AD4056 REF pin is as low as possible to pre-

vent VREF settling issues. Place a low effective series resistance

(ESR) decoupling capacitor as close to the AD4050/AD4056

REF pin as possible (see the Reference Circuit Design section).

Use wide traces between the voltage reference and the AD4050/

AD4056 REF pin.

►

Place the RC kickback filter capacitors as close to the IN+ and

IN− pins as possible (see the Analog Front-End Design section).

►

Place the supply decoupling capacitors as close to the VDD,

CLDO, and VIO pins as possible (see the Power Supplies

section).

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