PIC16F1507-ESLASHSS. datasheet(172/278 Pages) MICROCHIP

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PIC16(L)F1507

DS40001586D-page 172

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21.2

Fixed Duty Cycle (FDC) Mode

In Fixed Duty Cycle (FDC) mode, every time the

accumulator overflows (NCO_overflow), the output is

toggled. This provides a 50% duty cycle, provided that

the increment value remains constant. For more

information, see Figure 21-2.

The FDC mode is selected by clearing the NxPFM bit

in the NCOxCON register.

21.3

Pulse Frequency (PF) Mode

In Pulse Frequency (PF) mode, every time the accumu-

lator overflows (NCO_overflow), the output becomes

active for one or more clock periods. Once the clock

period expires, the output returns to an inactive state.

This provides a pulsed output.

The output becomes active on the rising clock edge

immediately following the overflow event. For more

information, see Figure 21-2.

The value of the active and inactive states depends on

the polarity bit, NxPOL in the NCOxCON register.

The PF mode is selected by setting the NxPFM bit in

the NCOxCON register.

21.3.1

OUTPUT PULSE WIDTH CONTROL

When operating in PF mode, the active state of the out-

put can vary in width by multiple clock periods. Various

pulse widths are selected with the NxPWS<2:0> bits in

the NCOxCLK register.

When the selected pulse width is greater than the

accumulator overflow time frame, the output of the

NCOx operation is indeterminate.

21.4

Output Polarity Control

The last stage in the NCOx module is the output polar-

ity. The NxPOL bit in the NCOxCON register selects the

output polarity. Changing the polarity while the inter-

rupts are enabled will cause an interrupt for the result-

ing output transition.

The NCOx output can be used internally by source

code or other peripherals. Accomplish this by reading

the NxOUT (read-only) bit of the NCOxCON register.

The NCOx output signal is available to the following

peripherals:

•CLC

•CWG

21.5

Interrupts

When the accumulator overflows (NCO_overflow), the

NCOx Interrupt Flag bit, NCOxIF, of the PIRx register is

set. To enable the interrupt event (NCO_interrupt), the

following bits must be set:

• NxEN bit of the NCOxCON register

• NCOxIE bit of the PIEx register

• PEIE bit of the INTCON register

• GIE bit of the INTCON register

The interrupt must be cleared by software by clearing

the NCOxIF bit in the Interrupt Service Routine.

21.6

Effects of a Reset

All of the NCOx registers are cleared to zero as the

result of a Reset.

21.7

Operation In Sleep

The NCO module operates independently from the

system clock and will continue to run during Sleep,

provided that the clock source selected remains

active.

The HFINTOSC remains active during Sleep when the

NCO module is enabled and the HFINTOSC is

selected as the clock source, regardless of the system

clock source selected.

In other words, if the HFINTOSC is simultaneously

selected as the system clock and the NCO clock

source, when the NCO is enabled, the CPU will go idle

during Sleep, but the NCO will continue to operate and

the HFINTOSC will remain active.

This will have a direct effect on the Sleep mode current.

21.8

Alternate Pin Locations

This module incorporates I/O pins that can be moved to

other locations with the use of the alternate pin function

moved and what their default locations are upon a

Reset, see Section 11.1 “Alternate Pin Function” for

more information.

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