PIC16F1507-ESLASHSS. datasheet(48/278 Pages) MICROCHIP

48 / 278 page

PIC16(L)F1507

DS40001586D-page 48

 2011-2015 Microchip Technology Inc.

5.3

Clock Switching

The system clock source can be switched between

external and internal clock sources via software using

the System Clock Select (SCS) bits of the OSCCON

using the SCS bits:

• Default system oscillator determined by FOSC

bits in Configuration Words

• Internal Oscillator Block (INTOSC)

5.3.1

SYSTEM CLOCK SELECT (SCS)

BITS

The System Clock Select (SCS) bits of the OSCCON

the CPU and peripherals.

• When the SCS bits of the OSCCON register = 00,

the system clock source is determined by value of

the FOSC<1:0> bits in the Configuration Words.

• When the SCS bits of the OSCCON register = 01,

the system clock source is the secondary

oscillator.

• When the SCS bits of the OSCCON register = 1x,

the system clock source is chosen by the internal

oscillator frequency selected by the IRCF<3:0>

bits of the OSCCON register. After a Reset, the

SCS bits of the OSCCON register are always

cleared.

When switching between clock sources, a delay is

required to allow the new clock to stabilize. These oscil-

lator delays are shown in Table 5-2.

5.3.2

CLOCK SWITCHING BEFORE

SLEEP

When clock switching from an old clock to a new clock

is requested just prior to entering Sleep mode, it is

necessary to confirm that the switch is complete before

the SLEEP instruction is executed. Failure to do so may

result in an incomplete switch and consequential loss

of the system clock altogether. Clock switching is

confirmed by monitoring the clock status bits in the

OSCSTAT register. Switch confirmation can be

accomplished by sensing that the ready bit for the new

clock is set or the ready bit for the old clock is cleared.

For example, when switching between the internal

oscillator with the PLL and the internal oscillator without

the PLL, monitor the PLLR bit. When PLLR is set, the

switch to 32 MHz operation is complete. Conversely,

when PPLR is cleared, the switch from 32 MHz

operation to the selected internal clock is complete.

TABLE 5-2:

OSCILLATOR SWITCHING DELAYS

Switch From

Switch To

Oscillator Delay

Any clock source

LFINTOSC

1 cycle of each clock source

HFINTOSC

s (approx.)

ECH, ECM, ECL

2 cycles

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