PIC16F1507-ESLASHSS. datasheet(30/278 Pages) MICROCHIP

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PIC16(L)F1507

DS40001586D-page 30

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3.4

PCL and PCLATH

The Program Counter (PC) is 15 bits wide. The low byte

comes from the PCL register, which is a readable and

writable register. The high byte (PC<14:8>) is not directly

readable or writable and comes from PCLATH. On any

Reset, the PC is cleared. Figure 3-3 shows the five

situations for the loading of the PC.

FIGURE 3-3:

LOADING OF PC IN

DIFFERENT SITUATIONS

3.4.1

MODIFYING PCL

Executing any instruction with the PCL register as the

destination simultaneously causes the Program

Counter PC<14:8> bits (PCH) to be replaced by the

contents of the PCLATH register. This allows the entire

contents of the program counter to be changed by

writing the desired upper seven bits to the PCLATH

PCL register, all 15 bits of the program counter will

change to the values contained in the PCLATH register

and those being written to the PCL register.

3.4.2

COMPUTED GOTO

A computed GOTO is accomplished by adding an offset to

the program counter (ADDWF PCL). When performing a

table read using a computed GOTO method, care should

be exercised if the table location crosses a PCL memory

boundary (each 256-byte block). Refer to Application

Note AN556, “Implementing a Table Read” (DS00556).

3.4.3

COMPUTED FUNCTION CALLS

A computed function CALL allows programs to maintain

tables of functions and provide another way to execute

state machines or look-up tables. When performing a

table read using a computed function CALL, care

should be exercised if the table location crosses a PCL

memory boundary (each 256-byte block).

If using the CALL instruction, the PCH<2:0> and PCL

registers are loaded with the operand of the CALL

instruction. PCH<6:3> is loaded with PCLATH<6:3>.

The CALLW instruction enables computed calls by com-

bining PCLATH and W to form the destination address.

A computed CALLW is accomplished by loading the W

The PCL register is loaded with the value of W and

PCH is loaded with PCLATH.

3.4.4

BRANCHING

The branching instructions add an offset to the PC.

This allows relocatable code and code that crosses

page boundaries. There are two forms of branching,

BRW

and BRA. The PC will have incremented to fetch

the next instruction in both cases. When using either

branching instruction, a PCL memory boundary may be

crossed.

If using BRW, load the W register with the desired

unsigned address and execute BRW. The entire PC will

be loaded with the address PC + 1 + W.

If using BRA, the entire PC will be loaded with PC + 1 +,

the signed value of the operand of the BRA instruction.

PCL

PCH

PCLATH

Instruction

with PCL as

Destination

GOTO,

CALL

CALLW

BRW

BRA

ALU result

OPCODE <10:0>

PC + W

PC + OPCODE <8:0>

Rev. 10-000042A

7/30/2013

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