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PIC16F1507-E/SS. 数据表(PDF) 67 Page - Microchip Technology |
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PIC16F1507-E/SS. 数据表(HTML) 67 Page - Microchip Technology |
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67 / 278 page  2011-2015 Microchip Technology Inc. DS40001586D-page 67 PIC16(L)F1507 REGISTER 7-4: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 — — — — — — CLC2IE CLC1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 CLC2IE: Configurable Logic Block 2 Interrupt Enable bit 1 = Enables the CLC 2 interrupt 0 = Disables the CLC 2 interrupt bit 0 CLC1IE: Configurable Logic Block 1 Interrupt Enable bit 1 = Enables the CLC 1 interrupt 0 = Disables the CLC 1 interrupt Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. |
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