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PIC16F1507-E/SS. 数据表(PDF) 62 Page - Microchip Technology |
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PIC16F1507-E/SS. 数据表(HTML) 62 Page - Microchip Technology |
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62 / 278 page  PIC16(L)F1507 DS40001586D-page 62 2011-2015 Microchip Technology Inc. FIGURE 7-3: INT PIN INTERRUPT TIMING Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 FOSC CLKOUT INT pin INTF GIE INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Interrupt Latency PC PC + 1 PC + 1 0004h 0005h Inst (0004h) Inst (0005h) Forced NOP Inst (PC) Inst (PC + 1) Inst (PC – 1) Inst (0004h) Forced NOP Inst (PC) — Note 1: INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: For minimum width of INT pulse, refer to AC specifications in Section 25.0 “Electrical Specifications”. 4: INTF is enabled to be set any time during the Q4-Q1 cycles. (1) (2) (3) (4) (1) |
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