PIC16F1507-ESLASHSS. datasheet(100/278 Pages) MICROCHIP

100 / 278 page

PIC16(L)F1507

DS40001586D-page 100

 2011-2015 Microchip Technology Inc.

TABLE 11-3:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

TABLE 11-4:

SUMMARY OF CONFIGURATION WORD WITH PORTA

WPUA: WEAK PULL-UP PORTA REGISTER

U-0

R/W-1/1

—

WPUA5

WPUA4

WPUA3

WPUA2

WPUA1

WPUA0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7-6

Unimplemented:

Read as ‘0’

bit 5-0

WPUA<5:0>

: Weak Pull-up Register bits(3)

= Pull-up enabled

= Pull-up disabled

Note 1:

Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.

The weak pull-up device is automatically disabled if the pin is configured as an output.

For the WPUA3 bit, when MCLRE = 1, weak pull-up is internally enabled, but not reported here.

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

on Page

ANSELA

—

—ANSA4

—

ANSA2

ANSA1

ANSA0

APFCON

—

T1GSEL

—

CLC1SEL

NCO1SEL

LATA

—

—LATA5

LATA4

—

LATA2

LATA1

LATA0

OPTION_REG

WPUEN

INTEDG

TMR0CS

TMR0SE

PSA

PS<2:0>

133

PORTA

—

RA5

RA4

RA3

RA2

RA1

RA0

TRISA

—

TRISA5

TRISA4

—(1)

TRISA2

TRISA1

TRISA0

WPUA

—

WPUA5

WPUA4

WPUA3

WPUA2

WPUA1

WPUA0

100

Legend:

= unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.

Note

Unimplemented, read as ‘1’.

Name

Bits

Bit -/7

Bit -/6

Bit 13/5

Bit 12/4

Bit 11/3

Bit 10/2

Bit 9/1

Bit 8/0

on Page

CONFIG1

13:8

—

—CLKOUTEN

BOREN<1:0>

—

7:0

MCLRE

PWRTE

WDTE<1:0>

—

FOSC<1:0>

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.

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