PIC16F1507-ESLASHSS. datasheet(46/278 Pages) MICROCHIP

46 / 278 page

PIC16(L)F1507

DS40001586D-page 46

 2011-2015 Microchip Technology Inc.

5.2.2.4

Peripheral Clock Sources

The clock sources described in this chapter and the

Timer’s are available to different peripherals. Table 5-1

lists the clocks and timers available for each peripheral.

5.2.2.5

Internal Oscillator Frequency

Selection

The system clock speed can be selected via software

using the Internal Oscillator Frequency Select bits

IRCF<3:0> of the OSCCON register.

The postscaled output of the 16 MHz HFINTOSC and

31 kHz LFINTOSC connect to a multiplexer (see

Figure 5-1). The Internal Oscillator Frequency Select

bits IRCF<3:0> of the OSCCON register (Register 5-1)

select the frequency output of the internal oscillators.

The IRCF<3:0> bits of the OSCCON register allow

duplicate selections for some frequencies. These dupli-

cate choices can offer system design trade-offs. Lower

power consumption can be obtained when changing

oscillator sources for a given frequency. Faster transi-

tion times can be obtained between frequency changes

that use the same oscillator source.

5.2.2.6

Internal Oscillator Clock Switch

Timing

When switching between the HFINTOSC and the

LFINTOSC, the new oscillator may already be shut

down to save power (see Figure 5-3). If this is the case,

there is a delay after the IRCF<3:0> bits of the

OSCCON register are modified before the frequency

selection takes place. The OSCSTAT register will

reflect the current active status of the HFINTOSC and

LFINTOSC oscillators. The sequence of a frequency

selection is as follows:

IRCF<3:0> bits of the OSCCON register are

modified.

If the new clock is shut down, a clock start-up

delay is started.

Clock switch circuitry waits for a falling edge of

the current clock.

The current clock is held low and the clock

switch circuitry waits for a rising edge in the new

clock.

The new clock is now active.

The OSCSTAT register is updated as required.

Clock switch is complete.

See Figure 5-3 for more details.

If the internal oscillator speed is switched between two

clocks of the same source, there is no start-up delay

before the new frequency is selected. Clock switching

time delays are shown in Table 5-2.

Start-up delay specifications are located in Table 25-8,

“Oscillator Parameters”.

TABLE 5-1:

PERIPHERAL CLOCK

SOURCES

ADC

●●

CLC

●●●●●●●

CWG

●●

NCO

●●

PWM

●●

PWRT

●

TMR0

●

TMR1

●●

TMR2

●

WDT

●

Note:

Following any Reset, the IRCF<3:0> bits

of the OSCCON register are set to ‘0111’

and the frequency selection is set to

500 kHz. The user can modify the IRCF

bits to select a different frequency.

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