PIC16F1507-ESLASHSS. datasheet(16/278 Pages) MICROCHIP

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PIC16(L)F1507

DS40001586D-page 16

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3.3

Data Memory Organization

The data memory is partitioned in 32 memory banks

with 128 bytes in a bank. Each bank consists of

(Figure 3-2):

• 12 core registers

• 20 Special Function Registers (SFR)

• Up to 80 bytes of General Purpose RAM (GPR)

• 16 bytes of common RAM

The active bank is selected by writing the bank number

into the Bank Select Register (BSR). Unimplemented

memory will read as ‘0’. All data memory can be

accessed either directly (via instructions that use the

file registers) or indirectly via the two File Select

Registers

(FSR).

See

Section

3.6 “Indirect

Addressing”

for more information.

Data memory uses a 12-bit address. The upper five bits

of the address define the Bank address and the lower

seven bits select the registers/RAM in that bank.

3.3.1

CORE REGISTERS

The core registers contain the registers that directly

affect the basic operation. The core registers occupy

the first 12 addresses of every data memory bank

(addresses x00h/x08h through x0Bh/x8Bh). These

registers are listed below in Table 3-2. For detailed

information, see Table 3-4.

TABLE 3-2:

CORE REGISTERS

Addresses

BANKx

x00h or x80h

INDF0

x01h or x81h

INDF1

x02h or x82h

PCL

x03h or x83h

STATUS

x04h or x84h

FSR0L

x05h or x85h

FSR0H

x06h or x86h

FSR1L

x07h or x87h

FSR1H

x08h or x88h

BSR

x09h or x89h

WREG

x0Ah or x8Ah

PCLATH

x0Bh or x8Bh

INTCON

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