PIC16F1507-ESLASHSS. datasheet(73/278 Pages) MICROCHIP

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DS40001586D-page 73

PIC16(L)F1507

FIGURE 8-1:

WAKE-UP FROM SLEEP THROUGH INTERRUPT

8.2

Low-Power Sleep Mode

This device contains an internal Low Dropout (LDO)

voltage regulator, which allows the device I/O pins to

operate at voltages up to 5.5V while the internal device

logic operates at a lower voltage. The LDO and its

associated reference circuitry must remain active when

the device is in Sleep mode.

Low-Power Sleep mode allows the user to optimize the

operating current in Sleep. Low-Power Sleep mode can

be selected by setting the VREGPM bit of the

VREGCON register, putting the LDO and reference

circuitry in a low-power state whenever the device is in

Sleep.

8.2.1

SLEEP CURRENT VS. WAKE-UP

TIME

In the Default Operating mode, the LDO and reference

circuitry remain in the normal configuration while in

Sleep. The device is able to exit Sleep mode quickly

since all circuits remain active. In Low-Power Sleep

mode, when waking up from Sleep, an extra delay time

is required for these circuits to return to the normal con-

figuration and stabilize.

The Low-Power Sleep mode is beneficial for applica-

tions that stay in Sleep mode for long periods of time.

The Normal mode is beneficial for applications that

need to wake from Sleep quickly and frequently.

8.2.2

PERIPHERAL USAGE IN SLEEP

Some peripherals that can operate in Sleep mode will

not operate properly with the Low-Power Sleep mode

selected. The LDO will remain in the Normal Power

mode when those peripherals are enabled. The Low-

Power Sleep mode is intended for use with these

peripherals:

• Brown-out Reset (BOR)

• Watchdog Timer (WDT)

• External interrupt pin/Interrupt-on-change pins

• Timer1 (with external clock source)

The Complementary Waveform Generator (CWG), the

Numerically Controlled Oscillator (NCO) and the Con-

figurable Logic Cell (CLC) modules can utilize the

HFINTOSC oscillator as either a clock source or as an

input source. Under certain conditions, when the

HFINTOSC is selected for use with the CWG, NCO or

CLC modules, the HFINTOSC will remain active

during Sleep. This will have a direct effect on the

Sleep mode current.

Please refer to sections Section 20.5 “Operation

During Sleep”

, 21.7 “Operation In Sleep” and 22.10

“Operation During Sleep”

for more information.

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CLKIN(1)

CLKOUT(2)

Interrupt flag

GIE bit

(INTCON reg.)

Instruction Flow

Instruction

Fetched

Instruction

Executed

PC + 1

PC + 2

Inst(PC) = Sleep

Inst(PC - 1)

Inst(PC + 1)

Sleep

Processor in

Sleep

Interrupt Latency(4)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h)

Inst(0005h)

Inst(0004h)

Forced NOP

PC + 2

0004h

0005h

Forced NOP

TOST(3)

PC + 2

Note

External clock. High, Medium, Low mode assumed.

CLKOUT is shown here for timing reference.

TOST = 1024 TOSC. This delay does not apply to EC, RC and INTOSC Oscillator modes.

GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.

Note:

The PIC16LF1507 does not have a con-

figurable

Low-Power

Sleep

mode.

PIC16LF1507 is an unregulated device

and is always in the lowest power state

when in Sleep, with no wake-up time pen-

alty. This device has a lower maximum

VDD

and

I/O

voltage

than

the

PIC16F1507.

See

Section

25.0 “Electrical

Specifications”

for

more information.

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