PIC16F1507-ESLASHSS. datasheet(149/278 Pages) MICROCHIP

149 / 278 page

 2011-2015 Microchip Technology Inc.

DS40001586D-page 149

PIC16(L)F1507

19.1

PWMx Pin Configuration

All PWM outputs are multiplexed with the PORT data

latch. The user must configure the pins as outputs by

clearing the associated TRIS bits.

19.1.1

FUNDAMENTAL OPERATION

The PWM module produces a 10-bit resolution output.

Timer2 and PR2 set the period of the PWM. The

PWMxDCL and PWMxDCH registers configure the

duty cycle. The period is common to all PWM modules,

whereas the duty cycle is independently controlled.

All PWM outputs associated with Timer2 are set when

TMR2 is cleared. Each PWMx is cleared when TMR2

is equal to the value specified in the corresponding

PWMxDCH (8 MSb) and PWMxDCL<7:6> (2 LSb) reg-

isters. When the value is greater than or equal to PR2,

the PWM output is never cleared (100% duty cycle).

19.1.2

PWM OUTPUT POLARITY

The output polarity is inverted by setting the PWMxPOL

bit of the PWMxCON register.

19.1.3

PWM PERIOD

The PWM period is specified by the PR2 register of

Timer2. The PWM period can be calculated using the

formula of Equation 19-1.

EQUATION 19-1:

PWM PERIOD

When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

•TMR2 is cleared

• The PWM output is active. (Exception: When the

PWM duty cycle = 0%, the PWM output will

remain inactive.)

• The PWMxDCH and PWMxDCL register values

are latched into the buffers.

19.1.4

PWM DUTY CYCLE

The PWM duty cycle is specified by writing a 10-bit

value to the PWMxDCH and PWMxDCL register pair.

The PWMxDCH register contains the eight MSbs and

the PWMxDCL<7:6>, the two LSbs. The PWMxDCH

and PWMxDCL registers can be written to at any time.

Equation 19-2 is used to calculate the PWM pulse width.

Equation 19-3 is used to calculate the PWM duty cycle

ratio.

EQUATION 19-2:

PULSE WIDTH

EQUATION 19-3:

DUTY CYCLE RATIO

The 8-bit timer TMR2 register is concatenated with the

two Least Significant bits of 1/FOSC, adjusted by the

Timer2 prescaler to create the 10-bit time base. The

system clock is used if the Timer2 prescaler is set to 1:1.

Figure 19-2 shows a waveform of the PWM signal when

the duty cycle is set for the smallest possible pulse.

FIGURE 19-2:

PWM OUTPUT

Note:

Clearing the PWMxOE bit will relinquish

control of the PWMx pin.

Note:

The Timer2 postscaler is not used in the

determination of the PWM frequency. The

postscaler could be used to have a servo

update rate at a different frequency than

the PWM output.

Note:

The PWMxDCH and PWMxDCL registers

are double buffered. The buffers are

updated when Timer2 matches PR2. Care

should be taken to update both registers

before the timer match occurs.

PWM Period

PR2

 1

 4TOSC 



(TMR2 Prescale Value)

Note:

TOSC = 1/FOSC

Note:

The Timer2 postscaler has no effect on

the PWM operation.

Pulse Width

PWM x DCH :PWMxDCL<7:6>





T OSC

 (TMR2 Prescale Value)

Note:

TOSC = 1/FOSC

Duty Cycle Ratio

PW M xDC H:PWMxDCL<7:6>



4 PR2



-----------------------------------------------------------------------------------

Pulse Width

TMR2 = PR2

TMR2 =

TMR2 = PWMxDC

FOSC

PWM

Rev. 10-000023A

7/30/2013

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