IP100A LF
Preliminary Data Sheet
10/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
PIN Descriptions (continued)
PIN NAME
PIN TYPE
PIN DESCRIPTION
PCI INTERFACE
(continued)
PERRN
IN/OUT
Parity Error, asserted LOW. The IP100A LF asserts PERRN when it
checks and detects a bus parity errors. When it is generating PAR output,
the IP100A LF monitors for any reported parity error on PERRN.
SERRN
OUTPUT
System Error, asserted LOW.
VDET
INPUT
Power Detect. The IP100A LF detects PCI bus power supply loss when
VDET is LOW.
EEPROM INTERFACE
EECS
OUTPUT
EEPROM Chip Select. EECS is asserted by the IP100A LF to access the
EEPROM. EECS is connected directly to the chip select input of the
EEPROM device.
EESK
OUTPUT
EEPROM Serial Clock. EESK is an output connected directly to the clock
input of the EEPROM device.
EEDI
OUTPUT
EEPROM Data Input. EEDI is an output connected directly to the data input
of the EEPROM device. This pin is shared with LED100N pin.
EEDO
INPUT
EEPROM Data Output. EEDO is an input connected directly to the data
output of the EEPROM device. This pin is shared with Duplex LED pin.
LED DRIVERS
LED_TXN
OUTPUT
Transmit Status LED. This pin will stay LOW during transmission period
and HIGH if no data or pulse is beening sent from IP100A LF.
LED_RXN
OUTPUT
Receiving Status LED. This pin will stay LOW during receiving period and if
no data has been received, the LED_RXN status will be HIGH.
LED_DPLXN OUTPUT
Duplex Status LED. LED_DPLXN is the duplex status LED driver. The
duplex status LED driver is LOW when the link is full duplex, and HIGH
when the link is half duplex. Additional functionality of the speed status
LED signal is based on the LEDMode bit of the AsicCtrl register.
TABLE 2 : IP100A LF Pin Descriptions
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