IP100A LF
Preliminary Data Sheet
32/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
BIT
BIT NAME
R/W
BIT DESCRIPTION
8
100BASE-TX Full
Duplex
R
1 = 100BASE-TX Full Duplex capable.
0 = Not 100BASE-TX Full Duplex capable.
7
100BASE-TX Half
Duplex
R
1 = 100BASE-TX Half Duplex capable.
0 = Not 100BASE-TX Half Duplex capable.
6
10BASE-T Full
Duplex
R
1 = 10BASE-T Full Duplex capable.
0 = Not 10BASE-T Full Duplex capable.
5
10BASE-T Half
Duplex
R
1 = 10BASE-T Half Duplex capable.
0 = Not 10BASE-T Half Duplex capable.
4..0
Selector Field
R
Selector Field
11.1.7 Phy Specification Control Register
Class............................. PHY Registers
Access Method ............. Accessed through PhyCtrl register
Register Address .......... 0x16
Default .......................... 0x03A4
Width ............................ 16 bits
BIT
BIT NAME
R/W
BIT DESCRIPTION
15:6
Reserved
5
AUTOMDIX_ON
RO
AutoCrossOver can be set to enabled by setting this bit to 1, even
when AN is disabled
4
FEF_DISABLE
R/W
Set high to disable the functionality of Far-End Fault when the
chip operates at fiber mode
0: Enable FEF
1: Disable FEF
3
REPEAT_MODE
R/W
Set high to let IP100A LF operate at repeat mode
0: Not Repeat mode
1: Repeat mode
2
JABBER_ENA
R/W
Set high to enable jabber detection mechanism when IP100A LF
operates at 10BASE-T
0: Disable
1: Enable
1
HEARTBEAT_ENA R/W
Set high to enable heartbeat detection mechanism when IP100A
LF operates at 10BASE-T
0: Disable
1: Enable
0
BYPASS_DSPRST R/W
Set high to disable DSP reset watch-dog timer
0: Not Bypass
1: Bypass
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