IP100A LF
Preliminary Data Sheet
33/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
11.1.8 Phy Debug Control Register
Class............................. PHY Registers
Access Method ............. Accessed through PhyCtrl register
Register Address .......... 0x17
Default .......................... 0x0000
Width ............................ 16 bits
BIT
BIT NAME
R/W
BIT DESCRIPTION
15:6
Reserved
RO
Reserved for future use
5
NWAY_SPEED_UP RW
Set high to speed up all timers during NWAY procedure
4
DSP_SPEED_UP
RW
Set high to speed up DSP training sequcences
3
FORCE_LINK
RW
Set high to force link-up
2
BYPASS_SCRAM
RW
Set high to bypass PCS scrambler/de-scrambler
1..0
NWAY_DEBUG_SE
L
RW
These 2 bits are used to select NWAY debug output
11.1.9 Phy Status Monitor Register
Class............................. PHY Registers
Access Method ............. Accessed through PhyCtrl register
Register Address .......... 0x18
Default .......................... 0x0000
Width ............................ 16 bits
BIT
BIT NAME
R/W
BIT DESCRIPTION
15
LDSP_SLEEPING
RO
When set to high, indicating IP100A LF is in link-down sleeping
mode
14
LINK_OK
RO
When set to high, indicating link status is OK
13
DESCRAM _LOCK RO
When set to high, indicating PCS de-scrambler is locked on data
12
10BASE_
POLARITY
RO
When set to high, indicating the cable polarity is reversal (this bit
is meaningful only chip operates at 10BASE-T)
11
RESLOVED
_SPEED
RO
To indicate the resolved speed mode
0: 10BASE-T
1: 100BASE-TX/FX
10
RESLOVED
_DUPLEX
RO
To indicate the resolved duplex mode
0: Half Duplex
1: Full Duplex
9
MDI/MDIX
RO
To indicate either at MDI or MDIX state
0: MDI (Not Crossover)
1: MDIX(Crossover)
8..0
NWAY_DEBUG
_OUT
RO
NWAY debug output
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