IP100A LF
Preliminary Data Sheet
70/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
11.5.7 FramesTransmittedOk
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset.............. 0x70
Default .......................... 0x0000
Width ............................ 16 bits
BIT
BIT NAME
R/W
BIT DESCRIPTION
7..0
FramesTransmitted-
OK
R/W
Frames Transmitted OK is a count of the number of frames that
are successfully transmitted. FramesTransmittedOk will wrap
around to zero after reaching 0xFFFF. See IEEE 802.3 Clause
30.3.1.1.2.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when FramesTransmittedOk reaches a value
of 0xC0. FramesTransmittedOk is enabled by writing a logic 1 to
the StatisticsEnable bit in the MACCtrl1 register.
A read of FramesTransmittedOk also clears the register.
11.5.8 FramesWithDeferredXmission
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset.............. 0x78
Default .......................... 0x00
Width ............................ 8 bits
BIT
BIT NAME
R/W
BIT DESCRIPTION
7..0
FramesWithDeferred-
Xmission
R/W
Frames with Deferred Transmit is a count of the number of
frames that must delay their first attempt of transmission because
the medium was busy. Frames involved in any collisions are not
counted by FramesWithDeferredXmission. FramesWithDeferred-
Xmission wrap around to zero after reaching 0xFF. See IEEE
802.3 Clause 30.3.1.1.9.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when FramesWithDeferredXmission reaches a
value of 0xC0. FramesWithDeferredXmission is enabled by writing
a logic 1 to the StatisticsEnable bit in the MACCtrl1 register.
A read of FramesWithDeferredXmission also clears the register.
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