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IP100ALF 数据表(PDF) 73 Page - List of Unclassifed Manufacturers

部件名 IP100ALF
功能描述  Integrated 10/100 Ethernet MAC PHY
PDF  97 Pages
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制造商  ETC2 [List of Unclassifed Manufacturers]
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标志 ETC2 - List of Unclassifed Manufacturers

IP100ALF 数据表(HTML) 73 Page - List of Unclassifed Manufacturers

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IP100A LF
Preliminary Data Sheet
73/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
11.5.13 MultipleCollisionFrames
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x76
Default .......................... 0x00
Width ............................ 8 bits
BIT
BIT NAME
R/W
BIT DESCRIPTION
7..0
MultipleCollision-
Frames
R/W
Multiple Collision Frames is a count of the number of frames that
are involved in more than one collision and are subsequently
transmitted successfully. MultipleCollisionFrames will wrap around
to zero after reaching 0xFF. See IEEE 802.3 Clause 30.3.1.1.4.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when MultipleCollisionFrames reaches a value
of 0xC0. MultipleCollisionFrames is enabled by writing a logic 1 to
the StatisticsEnable bit in the MACCtrl1 register.
A read of MultipleCollisionFrames also clears the register.
11.5.14 OctetsReceivedOk
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x68
Default .......................... 0x00000000
Width ............................ 32 bits (accessible as 2, 16 bit words)
BIT
BIT NAME
R/W
BIT DESCRIPTION
19..0
OctetsReceivedOk
R/W
Octets Received OK is the count of the number of data and
padding octets in frames that are successfully received.
OctetsReceivedOk does not include frames received with frames
too long, FCS, length or alignment errors, or frames lost due to
internal MAC sublayer error (i.e. overrun). OctetsReceivedOk will
wrap around to zero after reaching 0xFFFFFFFF. See IEEE
802.3 Clause 30.3.1.1.14.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when OctetsReceivedOk reaches a value of
0xC0. OctetsReceivedOk is enabled by writing a logic 1 to the
StatisticsEnable bit in the MACCtrl1 register.
A read of OctetsReceivedOk also clears the register.
31..20
Reserved
N/A
Reserved for future use.



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