IP100A LF
Preliminary Data Sheet
76/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
11.6.1 CacheLineSize
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x0c
Default .......................... 0x00
Width ............................ 8 bits
BIT
BIT NAME
R/W
BIT DESCRIPTION
7..0
CacheLineSize
R/W
Cache Line Size. The system BIOS writes the system’s cache line
size into CacheLineSize. The host system uses CacheLineSize to
optimize PCI bus master operation (choosing the best memory
command, etc.). The value in CacheLineSize represents the
number of double words in a cache. CacheLineSize values must
be a power of two, from 0x04 to 0x80 (giving a range of 16 to 512
bytes). CacheLineSize values which are not a power of two,
between 4 and 128 are interpreted as 0x00.
11.6.2 CapId
Class............................. LAN PCI Configuration Registers, Power Management
Base Address ............... PCI device configuration header start
Address Offset .............. 0x50
Default .......................... 0x01
Width ............................ 8 bits
BIT
BIT NAME
R/W
BIT DESCRIPTION
7..0
CapId
R
Capabilities ID. CapId indicates the type of the capability data
structure for the IP100A LF. CapId is set to the value 0x01 to
indicate a PCI Power Management structure.
11.6.3 CapPtr
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x34
Default .......................... 0x50
Width ............................ 8 bits
BIT
BIT NAME
R/W
BIT DESCRIPTION
7..0
CapPtr
R
Capabilities Pointer. CapPtr indicates the beginning of a chain of
registers which describe enhanced functions. CapPtr register
returns 0x50, which is the address of the first in a series of power
management registers.
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