IP100A LF
Preliminary Data Sheet
71/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
11.5.9 FramesWithExcessiveDeferal
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x7a
Default .......................... 0x00
Width ............................ 8 bits
BIT
BIT NAME
R/W
BIT DESCRIPTION
7..0
FramesWithExcessi
veDeferal
R/W
Frames with Excessive Deferrals counts the number of frames
that deferred for an excessive period of time (exceeding the defer
limit). FramesWithExcessiveDeferal is only incremented once per
LLC frame. FramesWithExcessiveDeferal will wrap around to
zero after reaching 0xFF. See IEEE 802.3 Clause 30.3.1.1.20.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when FramesWithExcessiveDeferal reaches a
value of 0xC0. FramesWithExcessiveDeferal is enabled by writing
a logic 1 to the StatisticsEnable bit in the MACCtrl1 register.
A read of FramesWithExcessiveDeferal also clears the register.
11.5.10 LateCollisions
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x75
Default .......................... 0x00
Width ............................ 8 bits
BIT
BIT NAME
R/W
BIT DESCRIPTION
7..0
LateCollisions
R/W
Late Collisions is a count of the number of times that a collision
has been detected later than 1 slot time into the transmitted
frame. LateCollisions will wrap around to zero after reaching
0xFF. See IEEE 802.3 Clause 30.3.1.1.10.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when LateCollisions reaches a value of 0xC0.
LateCollisions is enabled by writing a logic 1 to the
StatisticsEnable bit in the MACCtrl1 register.
A read of LateCollisions also clears the register.
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