IP100A LF
Preliminary Data Sheet
3/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
Contents
Features....................................................................................................................................................... 1
General Description..................................................................................................................................... 1
Block Diagram ............................................................................................................................................. 2
Contents ...................................................................................................................................................... 3
Revision History........................................................................................................................................... 6
1
PIN Designations .................................................................................................................................. 7
2
PIN Diagram.......................................................................................................................................... 8
3
PIN Descriptions ................................................................................................................................... 9
PIN Descriptions
(continued)................................................................................................................... 10
PIN Descriptions
(continued)................................................................................................................... 11
4
Acronyms and Glossary...................................................................................................................... 13
5
Standards Compliance........................................................................................................................ 13
6
Functional Description ........................................................................................................................ 13
6.1
Media Access Control............................................................................................. 13
6.2
Physical Layer ........................................................................................................ 14
6.3
On-Chip Voltage Regulator..................................................................................... 14
6.4
PCI Bus Interface.................................................................................................... 14
6.5
TxDMA Logic .......................................................................................................... 14
6.6
TxFIFO.................................................................................................................... 15
6.7
RxDMA Logic.......................................................................................................... 15
6.8
RxFIFO ................................................................................................................... 15
6.9
EEPROM Interface ................................................................................................. 15
7
Operation ............................................................................................................................................ 16
7.1
Initialization ............................................................................................................. 16
7.2
Register Programming............................................................................................ 16
7.3
TxDMA and Frame Transmission........................................................................... 17
7.4
Frame Reception and RxDMA................................................................................ 19
7.5
Interrupts................................................................................................................. 22
8
Statistics.............................................................................................................................................. 22
8.1
Transmit Statistics .................................................................................................. 22
8.2
Receive Statistics ................................................................................................... 23
9
PCI Bus Master Operation .................................................................................................................. 23
10 Power Management............................................................................................................................ 24
10.1
Wake Event............................................................................................................. 27
10.2
Power Down ........................................................................................................... 27
11 Registers and Data Structures............................................................................................................ 28
11.1
PHY Registers ........................................................................................................ 28
11.1.1
Control Register...................................................................................................... 28
11.1.2
Status Register ....................................................................................................... 29
11.1.3
PHY Identifier 1....................................................................................................... 30
11.1.4
PHY Identifier 2....................................................................................................... 30
11.1.5
Auto-Negotiation Advertisement............................................................................. 31
11.1.6
Auto-Negotiation Link Partner Ability...................................................................... 31
11.1.7
Phy Specification Control Register ......................................................................... 32
11.1.8
Phy Debug Control Register ................................................................................... 33
11.1.9
Phy Status Monitor Register................................................................................... 33
11.1.10
SCA Settings .......................................................................................................... 34
11.2
DMA Data Structures.............................................................................................. 35
11.2.1
RxDMAFragAddr .................................................................................................... 35
11.2.2
RxDMAFragLen ...................................................................................................... 36
11.2.3
RxDMANextPtr ....................................................................................................... 36
11.2.4
RxFrameStatus....................................................................................................... 36
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