IP100A LF
Preliminary Data Sheet
69/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
11.5.5 FramesLostRxErrors
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x79
Default .......................... 0x00
Width ............................ 8 bits
BIT
BIT NAME
R/W
BIT DESCRIPTION
7..0
FramesLostRxErrors R/W
Frames Lost Due to Receive Errors is a count of the number of
frames that should have been received (the destination address
matched the filter criteria) but experienced a receive FIFO
overrun error (the receive FIFO does not have enough free space
to store the received data). FramesLostRxErrors only includes
overruns that become apparent to the host system, and does not
include frames that are completely ignored due to a completely
full receive FIFO at the beginning of frame reception.
FramesLostRxErrors will wrap around to zero after reaching
0xFF. See IEEE 802.3 Clause 30.3.1.1.15.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when FramesLostRxErrors reaches a value of
0xC0. FramesLostRxErrors is enabled by writing a logic 1 to the
StatisticsEnable bit in the MACCtrl1 register.
A read of FramesLostRxErrors also clears the register.
11.5.6 FramesReceivedOk
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x72
Default .......................... 0x0000
Width ............................ 16 bits
BIT
BIT NAME
R/W
BIT DESCRIPTION
7..0
FramesReceivedOk R/W
Frames Received OK is the count of the number of frames that
are successfully received. FramesReceivedOk does not include
frames received with frames too long, FCS, length or alignment
errors, or frames lost due to internal MAC sublayer error (i.e.
overrun). FramesReceivedOk will wrap around to zero after
reaching 0xFFFF. See IEEE 802.3 Clause 30.3.1.1.5.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when FramesReceivedOk reaches a value of
0xC0. FramesReceivedOk is enabled by writing a logic 1 to the
StatisticsEnable bit in the MACCtrl1 register.
A read of FramesReceivedOk also clears the register.
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